3-D IC can significantly alleviate the interconnect problem coming with the decreasing feature size and increasing integrated density. In this work, we concentrate on the 3-D IC floorplanning. It is proved that the number of configuration of 3-D floorplans is less than that of planar floorplans. Sequence Pair is extended (P-SP) to represent 3-D IC floorplans. A new solution perturbation method Remove and Insertion (RI) is implemented based on the technique of enumerating insertion points in P-SP, which is used in the traditional simulated annealing algorithm. The experimental results demonstrate the efficiency and the effectiveness of the proposed method.