A 62.5 Gb/s multi-standard SerDes IC
This paper describes a 20-lane 62.5 Gb/s SerDes designed as an interface between the 40G, or quad 10G Optics, and a downstream framer device. Transmit and receive clocks are derived from an LC-based PLL with a wideband RMS jitter below 2.5 ps. Timing recovery uses a 2/sup nd/ order loop and includes over-sampled /spl Delta//spl Sigma/ techniques to achieve both narrowband filtering and excellent jitter tolerance. To support backplane applications, line driver and receiver incorporate preemphasis and equalization respectively.