A VLSI filter architecture for digital HDTV codecs
The authors describe a compact VLSI implementation of fast pipelined two-dimensional FIR filters. A polyphase architecture is presented. The filter bank makes special use of coefficients which are in powers-of-two. This leads to an interest scheme where only shift and add operations are compared. A novel design strategy has been used to speed up the algorithm, as well as a novel adder. Internally, the speed achieved is around 200 MHz.<<ETX>>