A 12-bit 200KS/s SAR ADC with a mixed switching scheme and integer-based split capacitor array
A low power successive approximation register ADC (SAR ADC) using a high performance integer-based split capacitor array combining with a mixed switching strategy is presented in this work. The split capacitor is chosen to be 2 times unit capacitance rather than the traditional non-integer value which is difficult to get. This array features high linearity, low area and power consumption. Besides, a mixed switching strategy combining the merged capacitor switching with monotonic switching is also used to save half of total capacitance. And a time domain comparator is used to achieve better offset performance. Implemented in a 0.18-μm CMOS technology, the proposed ADC is measured to have a 65.5 dB signal-to-noise-and-distortion ratios(SNDR) which leads to a 10.6 effective number of bits(ENOB) at 200KS/s sampling rate. Its power consumption is 1.49-μW and figure of merit (FOM) is only 4.87 fJ/c-s at a voltage supply of 0.9V.