Field programmable gate array implementation of a generalized decoder for structured low-density parity check codes
This work describes a generalized decoder implementation for structured low-density parity check (LDPC) codes. The decoder features low logic consumption, efficient memory management, and full parameterization for reconfiguration. The goal is to provide a unified solution for fast evaluation of a broad class of structured LDPC codes utilizing the properties of field programmable gate arrays (FPGA): high speed and configurability. As a fully reconfigurable core, it is ready to be used in different applications to lower the design to market time. The throughput and resource consumptions are evaluated.