Current switched Josephson latching logic gates with sub-100ps delays
This paper describes the fabrication and testing of Josephson latching logic gates with an average delay per gate of between 37 to 96 picoseconds, depending on gate design. The gates are of the type developed by Fulton, Pei, and Dunkleberger. The gates employ two 7 micron square Josephson tunnel junctions and a small resistor in a loop. Series chains of 30 to 90 gates were tested. The control current from a previous gate is added to the bias current of the first junction in a gate and causes it to switch out of the zero voltage state. The second junction then switches and diverts most of the bias current to the fanout line. The second junction also diverts the control current from the previous gate through the small resistor to provide isolation between input and output. The experimentally measured margins and the sources of gate delay are discussed.