A novel 25V DDD NMOS design in 500–700V ultra high voltage BCD process
This article reports a high voltage DDD NMOS with 25V operating voltage and 40V breakdown voltage. Usually the DDD MOS in the logic process has a typical breakdown voltage lower than 18V. The further application requirement in higher breakdown voltage adopts LDMOS structures. In order to achieve high enough on-state breakdown voltage, the DDD NMOS presented in this paper has relatively high (about 1e13/cm2) doping level in the diffused drain region. In the case of the diffusion drain region with high level doping, the off-state breakdown voltage is affected, but the DDD NMOS in this paper adopts a novel design. Thus, the on/off-state breakdown voltage can reach 40V. The optimized device has excellent input/output characteristics and excellent on-resistance characteristics. The Ioff of the device is slightly larger and will be further optimized.