MASSIVELY PARALLEL ARCHITECTURE FOR AN UNSUPERVISED SEGMENTATION MODEL
In this paper we propose the structure of a novel massively parallel system-on-chip (SoC) architecture for a state-of-the-art probabilistic image segmentation model. This probabilistic model is formulated on a regular Markovian pixel grid. The unique combination of algorithmic robustness, SoC and real-time processing capabilities provides a new type of image processing systems in realworld applications. The model and the SoC architecture are extensively tested by natural images. Some chip design examples are also included to finalize the contribution.