A DC-11.5 GHz Low-Power, Wideband Amplifier Using Splitting-Load Inductive Peaking Technique
A DC-11.5 GHz low-power amplifier is developed in commercial 0.13 mum, CMOS technology. This amplifier design is based on a three-stage shunt-feedback inverter-configuration with splitting load inductive peaking technique. The peaking inductor is placed at the gate of the nMOS to compensate gain roll-off of the inverter stage and extend its operating bandwidth. This amplifier achieves a gain flatness of 13.21 dB from dc to 11.5 GHz with I/O return losses better than 17 dB at a power consumption of 9.1 mW. The measured noise figure is less than 5.6 dB between 1-11 GHz. The output P1 dB is 8 dBm and input third-order intercept point is 10 dBm. The total chip size is 0.34 mm2 including all testing pads, with a core area of only 0.08 mm2.