Design of A Low Power High Entropy Chaos-Based Truly Random Number Generator
This paper presents a low power high entropy design of a truly random number generator based on a simple chaotic map of the Bernoulli shift, which is extended to keep robustness in practical implementation. The map is accurately realized by switched-current techniques, and a pipelined architecture post-processed by simple XOR circuits is used to improve the throughput and the entropy. The whole design is implemented in UMC 0.18 mum CMOS mixed signal process, and the statistical properties are investigated by simulations. The power consumption is 3.024 mW and the truly random output bit rate is 20 Mbit/s