Design of a transistor-mismatch-insensitive switched-current memory cell
In this paper, we present a new and efficient switched-current memory cell consisting of six MOS transistors. A charge re-adjusting procedure is implemented in the memory cell to ensure an acceptable processing accuracy. Functionally, the current memory is insensitive to transistor parameter mismatch. The cell is currently under fabrication using 1.5-/spl mu/m p-well single-poly technology with an area of about 50/spl times/25 /spl mu/m/sup 2/. Applications of the proposed memory cell for the design of a multi-purpose analog signal processing operator are also discussed.