ULSI design-for-manufacturability: a yield enhancement approach
Yield enhancement is a quintessential objective of the
semiconductor industry. With diminishing feature size and increasing
chip area, the amount of “functional” silicon on a chip is
too expensive to discard in the event of short- and open-circuit faults.
Designing chips with high tolerance against faults, therefore, holds
great promise for profitable manufacturing in the semiconductor
industry. In this paper, we present an algorithm for integrated circuit
yield enhancement in the routing phase of layout synthesis. The focus is
on detailed routing. The proposed algorithm reduces layout critical area
for short circuits due to two-dimensional spot defects. Critical area
reduction is achieved in both horizontal and vertical layers without any
penalties on net length or channel density. Results show yield
improvement of 15-25% from the application of the proposed algorithms