An Area-efficient VLSI Implementation of CA-2D-VLC Decoder for AVS
Context-based adaptive 2D-VLC (CA-2D-VLC) is adopted by AVS. In this paper, we present an area-efficient VLSI implementation of CA-2D-VLC decoder. Data compression storage (DCS) method is proposed in memory optimization for VLC tables and a reduction of 30% in on-chip memory cost is achieved. Furthermore, an Exp-Golomb decoder is developed with codeword segmentation decoding (CSD) method, which saves 70% hardware cost compared with the prior work. Synthesized with 0.18 mum CMOS standard-cell library, the overall hardware cost of the proposed CA-2D-VLC decoder is 1540 gates at the clock frequency constraint of 180MHz. With an average throughput of one symbol per cycle, the proposed design is suitable for cost-aware and high-resolution AVS video decoding applications. Though designed for AVS originally, the proposed architecture can be adapted to other coding standards easily.