BEOL yield predictions for SIA roadmap
Interconnect-related effects are a major constraint on the ability to achieve the goals for integration and performance projected by the SIA National Technology Roadmap for Semiconductors. As CMOS technology moves from 0.35 /spl mu/m to 0.1 /spl mu/m minimum feature sizes, minimum interconnect pitches are projected to shrink from 1.0 /spl mu/m to 0.27 /spl mu/m. Several factors may make BEOL yield a dominant concern in submicron manufacturing. Since both microprocessor (logic) transistor densities and chip areas are projected to grow from 4 M/cm/sup 2/ and 250 mm/sup 2/ to 50 M/cm/sup 2/ and 520 mm/sup 2/, the difficulty of interconnecting devices becomes much greater. Solving this wireability problem requires significant increases in the number of wiring levels on a chip. Shrinking interconnect pitches, an increased number of wiring levels, and increased chip area all combine to reduce BEOL yield. To achieve 90% product yield the SIA roadmap proposes substantial reductions in defect density. This paper predicts defect density requirements and wiring strategies which combine high performance with high yield as minimum feature sizes shrink from 0.35 /spl mu/m to 0.1 /spl mu/m. Predictions are made using a CAD tool, RIPE, the Rensselaer Interconnect Performance Estimator, which predicts the effects of interconnect technology, system design, and wiring strategy on wireability, performance, power, and BEOL yield. We predict about 99% BEOL yield using the SIA proposals for defect density. Significantly higher defect densities should give acceptable yields.