A 100 MHz macropipelined CISC CMOS microprocessor
A macropipelined CISC microprocessor implemented in a 0.75- mu m CMOS 3.3-V three-metal-layer technology is described. The 1.3 M-transistor custom chip measures 1.62*1.46 cm/sup 2/, dissipates 18 W (peak), and is packaged in a 339-pin PGA. The chip implements a macroinstruction pipeline to execute the instruction set of a popular CISC minicomputer. A block diagram of the major functional units is shown along with die micrograph.<<ETX>>