A 68.1-to-73.8GHz E-band low phase noise QPLL with amplifier feedback QVCO in 65-nm CMOS
A fully integrated 68.1–73.8GHz E-band low phase noise quadrature phase-locked loop (QPLL) is proposed. The quadrature voltage-controlled oscillator (QVCO) with a symmetrical coupling network formed by diode-connected transistors is used to reduce the phase error. In order to improve the oscillation frequency and reduced the phase noise, a feedback network composed of buffer amplifiers and capacitors is introduced to the QVCO. The locking-range divider chain of PLL consists of an injection-locked frequency divider (ILFD) with a 3-bit binary-weighted switch-capacitor bank, current mode logic (CML) dividers, and a multiple modulus divider (MMD). The proposed circuit was designed in a 65-nm CMOS process, and the QVCO achieves a tuning range of 8% from 68.1GHz to 73.8GHz with a phase noise of −95dBc/Hz at 1MHz offset while consuming only 12.5mW. The QPLL achieves an excellent phase noise of −93 dBc/Hz at 1MHz offset during the range, consuming 37.1mW of power and with a FoM of −174.1dBc/Hz.