Automated Coverage Register Access Technology on UVM Framework for Advanced Verification
VLSI Designs are getting more complex with the advancements in technologies. These design rules are forcing a large number of components on a single chip. The number of registers is also increasing in SOC/IP designs. The conventional verification techniques fail to provide consistent results when design consists of a large number of registers. The proposed architecture establishes a platform to automate the verification of complex intellectual properties with multiple register access. It improvises the results as compared to SystemVerilog and conventional Universal Verification Technology (UVM) testbench. This paper focuses on advanced verification scenarios using coverage automation and Register Access Technology (RAT) on UVM verification environment. The proposed testbench automation incorporates all necessary attributes including the functional correctness of register values. The work exposes the register database in multiple register SoC/IP design. The proposed testbench justifies the functional coverage and fast execution of verification flow as compared to conventional verification methods.