A new low power building block cell for adders
One of the main factors in developing low power systems is reducing power consumption at the circuit design level and the module building block levels in the design. Following this strategy a low power and high speed full adder cell with the minimum number of transistors has been developed. The proposed cell is a combination of a 3-input XOR gate and transmission gates. The proposed cell has been compared to the other three basic common cells. An extensive analysis of the four architectures of adders, namely carry ripple, carry skip, carry select and carry lookahead has proved the superiority of the proposed cell.