Hysteresis Reduction in Negative Capacitance Ge PFETs Enabled by Modulating Ferroelectric Properties in HfZrOx
We experimentally demonstrate that hysteresis of negative capacitance (NC) Ge pFETs is reduced through modulating the ferroelectric properties in HfZrO<sub><italic>x</italic></sub> (HZO) by changing the post annealing temperature. As annealing temperature varies from 350 °C to 450 °C, HZO exhibits a significant increasing in the ratio of remnant polarization <inline-formula> <tex-math notation="LaTeX">$P_{r}$ </tex-math></inline-formula> to coercive field <inline-formula> <tex-math notation="LaTeX">$E_{c}$ </tex-math></inline-formula>, which results in the improvement of the magnitude of ferroelectric NC <inline-formula> <tex-math notation="LaTeX">$C_\mathrm{FE}$ </tex-math></inline-formula>, therefore contributing to the reduction of hysteresis of the ferroelectric NC Ge transistors. It is also reported that the NC Ge transistor annealed at 450 °C has a small hysteresis of 0.10 V, and achieves the improved SS and <inline-formula> <tex-math notation="LaTeX">$I_\mathrm{DS}$ </tex-math></inline-formula> compared to control device without HZO.