Low power FIR filter FPGA implementation based on distributed arithmetic and residue number system
In this paper, several low power techniques are proposed for the FPGA implementation of a distributed arithmetic and residue number system-based FIR filter. Two algorithms are proposed to reduce the size of the residue-to-binary converter, which is the crucial part of the system. The area, speed and power consumption of the filter is improved accordingly. Furthermore, a lookup table (LUT) partition technique is presented such that the most frequently accessed locations are stored in a smaller memory. The power consumption of the LUTs is reduced because accesses to smaller LUTs dissipate less power. The implementation results show a 20% power reduction by using the proposed methods.