Parallel programmable video co-processor design
Modern video applications call for computationally intensive data processing at very high data rate. In order to meet the high-performance/low-cost constraints, the state-of-the-art video processor should be a programmable design which performs various tasks in video applications without sacrificing the computational power and the manufacturing cost in exchange for such flexibility. In this paper, we present a programmable video co-processor design that is capable of performing FIR/IIR filtering, subband filtering, and most discrete orthogonal transforms (DT), for the host processor in video applications. The computational speed of this co-processor is as fast as that of ASIC designs which are optimized for individual specific applications. We also show that the system can be easily reconfigured to perform multirate FIR/IIR/DT operations at negligible hardware overhead. Hence, we can either double the processing speed on the fly based on the same processing elements, or apply this feature to the low-power implementation of this co-processor.