Characterization and improvement of immersion process defectivity in memory device manufacturing
As integrated circuit (IC) industry steps into immersion lithography's era, defectivity in photolithography becomes more complex which requires more efforts in the analysis and solution finding when compared to traditional dry lithographic process. In this paper, we focus on one type of immersion defects from memory or flash memory devices with typical mask layouts. Since the use of self-aligned double patterning (SADP) or other double patterning techniques, the original single pattern layer has to be split into 2 mask layers: logic area vs cell area. One characteristic of such split process is that the total mask transmission rate (TR) is above 70%, with both big open areas and a pattern area with a transmission rate close to 50%. This means that its defects characteristics can be a little different from logic devices. We have found that memory device is easier to suffer photoresist (PR) residue defects with center ring-like map. We have analyzed its underlying mechanisms and found optimized approaches to improve it by tuning parameters in development and rinse recipe. The results of our study will be presented and discussed.