VLSI Architecture for Low-Complexity Motion Estimation in H.264 Multiview Video Coding
This paper presents a VLSI architecture for a low complexity motion estimation algorithm, referred to as Slim264, for multiview video coding extension of H.264. Algorithmic modifications are introduced to obtain a fully parallel computational structure able to meet the throughput requirements of high resolution and high frame rate videos. High parallelism is achieved by predicting small blocks, i.e. 4x4 pixel blocks, in parallel and then adding them up in order to get Sum of Absolute Differences (SADs) of large block sizes. The predictor is able to support high resolution videos i.e. 1080p. The modified algorithm shows promising PSNR results with respect to full search algorithm. The predictor is synthesized with a clock frequency of 200 MHz, occupying an area of 0.49 mm2, on 90-nm Standard Cell ASIC technology.