Design of prioritized LRU circuit for shared cache in real-time computer systems
This paper presents a prioritized LRU (least recently used) cache replacement circuit that directly accomplish the prioritized operation inside the cache circuits, which significantly reduces cache access latency. The performance, hardware and power overheads due to incorporating prioritized operations in cache circuits are investigated based on a 65nm CMOS technology. It shows the design of prioritized cache has very low overhead compared to the conventional cache circuit. The presented circuit technique will lead to more effective prioritized cache implementations and benefit the development of high-performance real-time systems.