Architecture and implementation of real-time 3D stereo vision on a Xilinx FPGA
Many applications from autonomous vehicles to surveillance can benefit from real-time 3D stereo vision. In the present work we describe a 3D stereo vision design and its implementation that exploits effectively the resources of a Xilinx Virtex-5 FPGA. The post place-and-route design achieved a processing rate of 87 frames per sec (fps) for 1920 × 1200 resolution. The hardware prototype system was tested and validated for several data sets with resolutions up to 400 × 320 and we achieved a processing rate of 1570 fps.