A DCT chip based on a new structured and computationally efficient DCT algorithm
A discrete cosine transform (DCT) algorithm and architecture that minimize both software and hardware costs are presented. The proposed approaches are either direct or indirect and are based on the decomposition of the DCT in three operations: permutation, fast Fourier transform, and rotation. The main characteristics of the VLSI implementation chosen for this DCT and inverse DCT algorithm are show. Its data path coupled with a twin-pages memory and its controller, which contains the microprograms of the DCT algorithm are described. The results in terms of data processing rate and silicon area are given.<<ETX>>