Thermal stability of PVD TiN gate and its impacts on characteristics of CMOS transistors
The effects of rapid-thermal annealing (RTA) after source/drain (S/D) implant on the characteristics of CMOS transistors with sputtered TiN gate were investigated. Our results indicate that n/sup +//p junctions need higher thermal budget than p/sup +//n junctions to achieve low leakage performance. It was also found from C-V measurements that the flat-band voltage and oxide thickness are both affected by the annealing treatment, especially for p-channel devices. A hump in the subthreshold characteristics of p-channel transistors is observed, due to the existence of a leakage path along the isolation edge. It is also shown that the agglomeration phenomenon is easier to incur during the high-temperature RTA step as the metal gate width becomes narrower. When this happens, gate oxide integrity is degraded, resulting in increased gate leakage of n-channel transistors.