Reducing Delay Uncertainty of On-Chip Interconnects by Combining Inverting and Non-Inverting Repeaters Insertion
Coupling capacitances between neighboring wires have a significant effect on performance and delay uncertainty of on-chip interconnects in deep submicron (DSM) technologies. We propose combining inverting and non-inverting repeater insertion to achieve a constant effective coupling capacitance for all possible input transitions. Unlike staggered repeater scheme, the increased wire resistance does not have any effect on our technique, and the performance is less sensitive to repeater placement variation. Simulations at the 90-nm node on a semi-global METAL5 layer show around 25% reduction in worst case delay and 86% delay uncertainty minimization