A packaged 43-Gb/s clock and data recovery IC
A packaged 43-Gb/s clock and data recovery circuit with 1:2 demux in a 1/spl mu/m InP SHBT technology is reported. A half-rate phase/frequency detector incorporating a four-phase LC-ring oscillator is implemented in the phase and frequency locked loop thus eliminating an external reference clock as a frequency acquisition aid. Measured pull-in and hold-in ranges are 0.9 GHz and 1.1 GHz, respectively, with a peak-to-peak clock jitter of 4.5 ps at 43-Gb/s input data rate.