Area Efficient Architecture for the Embedded Block Coding in JPEG 2000
An area efficient architecture for the embedded block coding in JPEG 2000 is implemented on a 1.23 mm2 die using 0.18 mum CMOS technology. This chip can support 16.7 MS/s lossless encoding. The area of the proposed architecture is only 1/6 of the conventional architectures while the throughput is the same as others. The proposed architecture has the highest performance comparing with other existing architectures according to the experimental results