Traffic-aware power-gating scheme for Network-on-Chip routers
Network-on-Chip technology has become very popular in the recent decade to address the scalability issue in multi-core processors. Developing the inter-connection network improves the performance of multi-core systems at the cost of additional power and design complexity. Power-gating of router buffers as the most power consuming part of Network-on-Chip has been proposed recently to reduce the static power consumption. However, power-gating has its own shortcomings in terms of delay and power overhead that can diminish the overall performance if it is not used in sync with the traffic flow. In this paper, a power management technique has been introduced to optimize the power-gating of router input buffers by utilizing an adaptive learning scheme to estimate the future traffic arrival. The proposed design intelligently invokes the power-gating signals to the router buffers based on the statistical estimation of the traffic inter-arrival times. Syncing the power-gating signals with the traffic arrival significantly reduces the power-gating overhead caused by: mandatory wake-up delay to route immediate traffic arrival and static power consumption due to prolonging idle state in anticipation of future arrival. The simulation results indicate that the proposed scheme has average 25% improvement in the static power consumption compared to previous works while it reduces the average packet latency by 35% in comparison to naive power-gating. It is worth mentioning that the overhead of power-gating has significantly decreased by 41% compared to the proposed scheme in [1].