Copper Via Plating in Three Dimensional Interconnects
This paper describes the development of deep via plating in silicon substrates. Straight walled and tapered vias were plated through photoresist openings usually with bumps plated on top of via. In the second section similar vias were completely or partly filled, in process called "barrel" plating, in the absence of photoresist. The latter process turned out to be more challenging as flat wafer surface strongly competes with vias for current. Tapered vias are flared at the top, making it easier to sputter a base metal and plate with copper without creating seam or pinch off effects. In straight vias, the copper fill was more difficult and overcoming pinch off effect more challenging. Different current waveforms were used for each via shape shown. The changing geometry of gradually filled vias also required multiple steps during each plating process. Three current modes were applied including straight DC, pulse DC, and periodic reverse pulse current.