A low power architecture for a new efficient block-matching motion estimation algorithm
This paper presents an exhaustive search algorithm for block matching motion estimation. The proposed algorithm reduces the computational load with successive elimination of non-candidate blocks in the search window. The proposed algorithm locates the global optima as located by the full search block-matching algorithm. This computational reduction leads to low-power VLSI implementation of the algorithm.. Also, it leads to faster efficient motion estimation procedure. The correctness of this algorithm and its complexity presented. Simulation results on benchmark video clips are presented.