Design and Analysis of High Performance Ballistic Nanodevice-Based Sequential Circuits Using Monte Carlo and Verilog AMS Simulations
In this paper, we propose a design of traditional sequential circuits using high performance Ballistic Deflection Transistor (BDT). BDT technology was developed and experimentally proven to operate at Terahertz frequencies. Different structures of BDTs have been developed successfully to realize combinational logic functionality. Monte Carlo (MC) simulations have been extensively used to study these structures. By taking into account the effect of surface charges and dielectrics, we are able to correctly reproduce the non-linear I-V transfer characteristics, to predict scaling down behavior and to estimate the very high switching speed. We then used a three parameter Gaussian peak as a predictive model for the BDT and integrated it with Verilog AMS module to confirm the functionality of the designed circuits. Finally, we used a recently developed level-sensitive D-latch using two-BDTs structure, to explore traditional sequential circuits such as Shift Registers (SRs), Frequency Divider and Johnson Ring Counter, which play a pivotal role in many processing systems as common datapath operators. The simulation results have indicated the correct logic functionality of the implemented sequential circuits.