A multiprocessor system for interframe hierarchical address-vector quantization
The authors report on an ongoing design and performance evaluation of an interframe hierarchical address-vector quantization (IHAVQ) system for coding a sequence of moving images. The image coding system exploits the inherent parallelism of the IHAVQ algorithm by using a tree-structured multiprocessor architecture for distributed motion-compensated image data. An implementation of the system using three TM5320C25 DSP microprocessors is described, and its performance is analyzed.<<ETX>>