A motion estimator for low bit-rate video codec
A novel component performing motion estimation is presented. This chip is designed based on the three-step hierarchical search block-matching algorithm and can be applied to image communication on ISDN (integrated services digital network) (H.261 standard), MPEG, TV transmission, HDTV (high-definition television), etc. The practical architectural design techniques and the chip features are discussed. This component has the following features: unified execution steps, low latency delay, low I/O bandwidth, regular hardware structure, and single-chip or cascaded configurations. >