Architecture and bus-arbitration schemes for MPEG-2 video decoder
An efficient MPEG-2 video decoder architecture together with several effective bus-arbitration schemes designed to meet the main profile at main level (MP@ML) real-time decoding requirement is presented. The overall architecture, as well as the design of major function-specific processing blocks (variable-length decoder, inverse two-dimensional discrete cosine transform unit, and motion-compensation unit), is discussed. A hierarchical and distributed controller approach is used, a bus-monitoring model for different bus-arbitration schemes to control external DRAM accesses is developed, and the system is simulated. Practical issues and buffer sizes are addressed and evaluated. With a 27 MHz clock, our architecture uses many fewer than the 667 cycles, the upper bound for the MP@ML decoding requirement, to decode each macroblock with a single external bus and DRAM.