ASIC implementation architecture for pulse shaping FIR filters in 3G mobile communications
This paper presents two system-on-chip oriented implementation architectures for pulse shaping FIR filters used in 3G mobile communications. One is the look-up-table based distributed arithmetic architecture and the other one a modified multiply and accumulation (MAC) implementation. Both schemes employ the pre-upsampling procedure to minimize the consumption of hardware resources. The proposed architectures have been prototyped with FPGA implementation and can be integrated directly to ASIC products.