Impact-factor-guided X-filling for peak power reduction during test
Peak power during testing system-on-chip (SoC) circuits is a challenging issue for both reliability and yield. Because test vectors always try to activate as many faults as possible in the capture cycles, peak power during test usually happens in these cycles. X-filling is one effective way to reduce transitions happened in capture cycles to reduce peak power during test. However, its efficiency is limited and needs well exploration. This paper proposes an X impact-factor-metric to estimate the impact of filling one X bit on other X bits in test cube. This metric is utilized to efficiently guide the X-filling to reduce the capture power. We call it impact-factor-Guided (IFG) X-filling. Experimental results on larger ISCAS'89 benchmark circuits show that the average and maximum capture power can be reduced through our IFG X-filling by 65% and 31% on average, respectively.