Systolic array architectures for full-search block matching motion estimation
We present various systolic architectures for full search block matching motion estimation. Along with one dimensional (N PE's) and two dimensional (N/sup 2/ PE's) systolic array architectures using 2N, 3N,... ...., N/sup 2/-N processing elements are also presented. Each of the architectures is analyzed and then compared with others in terms of power consumption, area, delay and noise. Simulation and analysis results of the architectures are presented. The results show the trade-off between the number of processing elements used, processing rate and power dissipation.