Current reference with temperature compensation for low power applications
This paper proposes an all CMOS current reference with temperature compensation for low power applications. An offset voltage between the gate terminals of two MOS transistors is utilized to improve the temperature dependency caused by the carrier mobility. The circuit is designed and simulated in 0.18 μm standard CMOS technology. With a 52 nA output current, the temperature coefficient is 60 ppm/°C in a temperature range from -40 °C to 85 °C, the maximum process corner deviation is ±3%, the line regulation is 1780 ppm/V with a supply voltage ranging from 0.95 V to 2.5 V.