A high speed pipelined FFT processor
The authors describe a novel modular design and a VLSI implementation of a bit-serial pipelined fast Fourier transform (FFT) coprocessor. The proposed architecture is based on a distributed hardwired control mechanism. The control of various subunits in the processor is done by local controllers and the synchronization of operations is provided by a global controller. This FFT processor is a custom-built chip which has a built-in self-test (BIST) capability. BIST is provided using a coprocessor to a microprocessor, and the data transfer is controlled by asynchronous signals. A prototype of the proposed processor was implemented in 3- mu m SCMOS technology; it can operate at a maximum frequency of 50 MHz. The chip is a 32-pin square package, and it has a total area of 2.2 cm/sup 2/.<<ETX>>