A Bayesian network-based framework with Constraint Satisfaction Problem (CSP) formulations for FPGA system design
In recent years, there has been a growing interest in IP-reuse for SoCs in order to bridge the gap between the silicon capacity and the design productivity. This research work investigates how our proposed methodology can be used to partition and schedule a JPEG encoder IP core onto an FPGA. We will also describe a novel Constraint Satisfaction Problem (CSP) formulations that are used in the proposed framework. At the same time, we will also demonstrate the effectiveness of CSP in the Bayesian Network-based framework.