A CMOS stress sensor chip with integrated signal processing circuits
This paper reports an integrated silicon CMOS stress sensor chip. The sensor chip integrates a 16×16 CMOS stress sensor array with decoders, subtraction circuits, capacitive feedback trans-impedance amplifiers (CTIA), correlated double sampling circuits (CDS), rail-to-rail followers, and a low dropout regulator (LDO) in a monolithic chip. Each stress sensing cell in the array has a dimension of 55 μm × 55 μm to achieve high spatial resolution. Full integration of stress sensor array with signal processing circuits significantly suppresses circuit noises, enabling the sensor chip to achieve excellent performance. Measurement results on linearity, repeatability, zero drift and full-scale drift show that the overall error of the sensor chip is around 1.5% full-scale output.