Analysis and enhancements for EBCOT in high-speed JPEG2000 architectures
Due to the advanced features of the JPEG2000 compression algorithm, hardware designs of the system often face great challenges in terms of reducing delay, power, and silicon area. This paper implements an architecture for Tier-1 of EBCOT in the JPEG2000 encoder that focuses on high speed. Through the design process, critical components that affect the speed of the system are identified and enhancements to reduce the delay are presented at the system and circuit levels. Simulations results show a 17% improvement in speed for some of these components.