On the VLSI implementation of real-time order statistic filters
Real-time implementation of an order-statistic filter (OSF) or ranked order filter requires the computation of the order statistic (ranked order) of the samples in a window which gets periodically updated with the arrival of a new sample(s). The authors give an algorithm for the computation of the running order statistic. A highly parallel architecture suitable for VLSI implementation is presented. The architecture is very versatile, with programmable window size and rank order. An expansion algorithm and its VLSI architecture, which permit the usage of two r-bit OSFs to implement an (r+1)-bit OSF, where r is the resolution of the input signal samples, are given. In a special case where one is satisfied with at most one LSB error, the hardware complexity of the proposed architecture can be reduced by almost one half. It is further shown how a VLSI chip incorporating the proposed architecture can be used as the basic building block in the real-time implementation of other forms of nonlinear filters. >