Timing Recovery Loop Delay Compensation by Optimal Loop Gains
Future data storage systems must cope with higher densities and lower signal-to-noise ratios. Decision-aided timing recovery loops will likely need a longer delay in the sequence detector to make reliable bit decisions. Loop delay degrades the dynamics of the phase-locked loop (PLL). In this paper we present a process to determine optimal gains for PLL with delay assuming that the timing drift is well modeled by a second order random walk. Simulation shows that the loss of lock rate from the proposed method is similar to the delay compensation method in [1, 2], with both approaches offering much lower loss of lock rates than conventional PLL without delay compensation. The simulation also shows there is an optimal delay. Method in [1, 2] adds components to the PLL, whereas no extra hardware is needed for the proposed method.