Noise model of indirect-feedback sigma-delta image sensors
A novel architecture for a CMOS image sensor that incorporates a column-level sigma-delta (ΣΔ) analog-to-digital converter is presented. An indirect-feedback readout architecture where the digital output of the ΣΔ modulator is accumulated by a digital counter and converted to an analog voltage that serves as the reference voltage to which the buffered photodiode voltage is compared is shown. A time-domain pixel simulator that enables assessment of major noise contributors in this type of imager is also presented. Theoretical calculations align with simulation results, showing a minimum readout noise of 2.18e- and a dynamic range of over 100dB. A prototype chip has been developed in TSMC's 0.35-μm technology and its performance will be assessed.