Large dynamic range high resolution digital delay generator based on FPGA
A novel digital delay generator (DDG) based on FPGA was designed with 4.4ms range and 65ps resolution. The time-to-digital conversion (TDC) utilizing dual tapped delay lines was implemented in the FPGA to accurately measure the time interval between the rising edge of the FPGA global clock and the input trigger pulse. And the time interval was compensated in the following circuits by a AD9501 chip. The counter in the FPGA delays coarse time and another AD9501 chip delays fine time. To increase the accuracy, self-test block was developed in the FPGA to avoid the deviation induced from bad INL and DNL of AD9501 chips. Finally, the jitter of the system tested by TEK (TDS7404) oscilloscope was 400ps.