VLSI architecture design for a fast parallel label assignment in binary image
We propose a new connected component labeling method based on a 3/spl times/4 window for a binary image. This method possesses parallel processing to achieve high speed operation. According to the proposed method, we design an efficient VLSI architecture which only uses two process elements and a class storage array to complete the whole label assignment after two raster scans. From experimental results, our design has better performance in terms of hardware cost and speed. This architecture has been verified on FPGA. It takes 6120 logic elements and its working frequency is about 80 MHz.