Circuits and Implementation of a Low-Power Embedded EEPROM Memory
A 2-Kbit low-power embedded EEPROM memory, which is based on SMIC 0.35 mum three-metal two-poly mixed signal CMOS technology with embedded EEPROM technology, has been developed. Key design techniques of power dissipation optimization for EEPROM memory are described. Optimizations of the current consumption for the charge pump circuit are treated in this paper. To optimize the read access power consumption, a new SA (sense amplifier) using voltage sensing is proposed