Negative Capacitance Ge PFETs for Performance Improvement: Impact of Thickness of HfZrOx
We report a comparative investigation of the negative capacitance (NC) Ge pFETs with different thicknesses of HfZrO<sub><italic>x</italic></sub> (HZO). Although the NC transistors with 6.6 nm HZO exhibit the sub-60 mV/decade subthreshold swing, the hysteresis inevitably occurs. The hysteresis-free characteristics are demonstrated in the NC Ge pFETs with 4.5 and 3.7 nm HZO. The influence of postannealing temperature on device performance is dependent on the thickness of HZO. With the postannealing at 450 °C, NC transistors with 4.5 and 3.7 nm HZO achieve 23% and 11% <inline-formula> <tex-math notation="LaTeX">${I}_{\textsf {DS}}$ </tex-math></inline-formula> improvement, respectively, over the control devices, at a <inline-formula> <tex-math notation="LaTeX">${V}_{\textsf {GS}}$ </tex-math></inline-formula>–<inline-formula> <tex-math notation="LaTeX">${V}_{\textsf {TH}}$ </tex-math></inline-formula> of −1.0 V and a <inline-formula> <tex-math notation="LaTeX">${V}_{\textsf {DS}}$ </tex-math></inline-formula> of –0.05 V. However, a higher postannealing temperature of 550 °C leads to the significant degradation in NC device with 4.5 nm HZO compared with the control device. It is further observed that, with the fixed HZO thickness and postannealing temperature, <inline-formula> <tex-math notation="LaTeX">${I}_{\textsf {DS}}$ </tex-math></inline-formula> of the NC Ge pFETs is improved as the <inline-formula> <tex-math notation="LaTeX">${C}_{G}$ </tex-math></inline-formula> peak gets increased.