A low power VLSI architecture for multistage interval-based motion estimation (MIME) algorithm
We present an algorithmic enhancement of the full-search block-matching algorithm for motion estimation. The proposed algorithm reduces the computational load by successively eliminating noncandidate blocks from the search window. The elimination process uses low bit-resolution blocks and it is applied in two stages for motion vector computation. This computational reduction leads to enhanced performance in terms of low power consumption and fast motion vector estimation. A low power VLSI implementation of the algorithm is also presented. Simulation results show that the new algorithm, at an average, eliminates more than 88% of the candidate blocks in the search window.