Optimal module set and clock cycle selection for DSP synthesis
The authors present a program to determine the optimal module set and clock cycle time of an application specific digital signal processor at the beginning of synthesis. This method systematically performs design space exploration in actual time and space domain. The module set can include single-cycle, multicycle or pipelined operators. The optimal clock cycle selection is done by scanning all suboptimal clock cycle values in an efficient way. The cost of hardware considers both the cost of the data path and that of the controller. Several examples are given to show the advantages of the approach.<<ETX>>