Hardware implementation of MPEG analysis and deblocking for video enhancement
In this work, we develop an architecture to implement a deblocking filter to improve the quality of video decoded from MPEG. The filter is controlled by the quantization scale parameter, which is derived from the decoded stream based on a novel algorithm. The hardware implementation is targeting an FPGA device similar to those currently used in post-processing units of high end flat panel TV sets. The designed filter shows good performance in terms of robust signal-to-noise ratio and its implementation meets the area and frequency constraints.