A 140GHz phase-locked loop with 14.3% locking range in 65-nm CMOS
A fully integrated THz phase-locked loop (PLL) is proposed. It is consists of a fundamental PLL and a frequency doubler. In order to improve the oscillation frequency and reduced the phase noise, a feedback network composed of buffer amplifiers and capacitors is introduced to the voltage-controlled oscillator (VCO). The wide locking-range divider chain of PLL consists of an injection-locked frequency divider (ILFD) with a 3-bit binary-weighted switch-capacitor bank, current mode logic (CML) dividers, a multiple modulus divider (MMD). The proposed circuit was designed in a 65-nm CMOS process, and the VCO achieves a tuning range of 16.4% from 66GHz to 76GHz with a phase noise of −97dBc/Hz at 1MHz offset while consuming only 6.5mW. After the VCO, a broadband high efficiency frequency doubler can make output frequency from 132GHz to 152GHz with the fundamental rejection is larger than 20dB. The PLL achieves an excellent phase noise of −86 dBc/Hz in 144GHz at 1MHz offset, consuming 40.1mW of power.