A Pipelined Memory-efficient Architecture for Ultra-long Variable-size FFT Processors
A scheme of ultra-long variable-size pipelined FFT processor is presented and a prototype is implemented with one FPGA, which may compute various 4n (n = 1 ~ 10) points FFT at a speed as high as 150 MHz. The solutions are to transform the one-dimension FFT to two-dimension repeatedly, and propose an efficient twiddle-factor memory compression method. Based on two techniques storage resource of FFT processor can be reduced largely.