Investigation on solder bump process polyimide cracking for wafer level packaging
Typical controlled collapse chip connection (C4) bump structurally composed of solder bump, Ni UBM and Cu/Ti sputtered film on the top side of Si wafer in which polyimide film patterned and coated onto wafer as a buffer layer between substrate and UBM for stress relief. C4 bump structure is widely used in high-performance device of semiconductor package industries for many years and has achieved good reliability performance. In the past experience, stress-induced polyimide crack would happen on low-k IC package and be associated with inter-layer dielectric (ILD) cracking during thermal process and resulting in reliability problem. In order to resolve polyimide cracking problem, this preliminary study is attempted to optimize the bumping process based on the experimental of C4 bump structure with Copper pad as polyimide underneath to simulate the key condition of bumping process. Three key parameters in process, curing temperature, reflow peak temperature and reflow cooling rate, were considered to differentiate the influence degree related to the thermal stress from coefficient of thermal expansion (CTE) mismatch. Focus ion beam (FIB) and finite element methods were separately employed for cranny observation and stress modeling. The result exhibits the cured polyimide cranny formed under the condition of higher curing temperature, higher reflow cooling rate. The dominant factor is polyimide curing temperature (PCT), and followed by reflow peak temperature (RPT) and reflow cooling rate (RCR), sequentially. The cranny on polyimide propagated to and around the round-shaped Ni undercut spot after reflow due to the thermal stress arising from CTE mismatch between the polyimide and contained metals. Low curing temperature (350°C) with lower modulus of elasticity, low reflow temperature (240°C) and slow cooling rate (2.9°C/s) allow polyimide to absorb more strain energy and flexibly adjust internal stress far from fracture stress.