Design and implementation of JPEG encoder IP core
A complete, low cost baseline JPEG encoder soft IP and its chip implementation are presented in this paper. It features user-defined, run-time reconfigurable quantization tables, highly modularized and fully pipelined architecture. A prototype, synthesized with COMPASS cell library, has been implemented in TSMC 0.6-/spl mu/m single-poly triple-metal process. It can run up to 40 MHz at 3.3 V. This IP can be easily integrated into various application systems, such as scanner, PC camera and color FAX, etc.