Structure generation and design of tracking ADCs
In this paper, a new model for a low power CMOS current-mode Tracking Analog-to-Digital Converter (ADC) is proposed. The model generates several designs that differ in power consumption and signal bandwidth specifications. As an example, A 6-bit ADC, with a maximum acquisition speed of 130 MHz, is implemented in a 1 V analog supply voltage. Spectre simulation results for the proposed tracking ADC verifying the analytical results are also given. It shows that the circuit consumes a static power of 0.63 mW and a dynamic power of 0.49 mW in a commercial 90 nm CMOS process.