System-level analysis for MPEG-4 decoding on a multi-processor architecture
The convergence of TV and new features such as Internet and games, requires a generic media-processing platform, that enables simultaneous execution of very diverse tasks, ranging from stream-oriented processing to highly data-dependent irregular processing with complex control. This paper presents the mapping of a Main-Visual profile MPEG-4 decoder for High-Definition (HD) video onto a flexible architecture platform. The hardware-software (HWSW) design is derived by analyzing a partitioning of distinct tasks within the application. The proposed implementation contains a hierarchy of processors, which are matched to the characteristics of the processing tasks. Additionally, we introduce a hierarchy in communication and memory for memory-bandwidth efficiency and flexibility for HW reuse. The architecture provides various trade-off possibilities (flexibility, extensibility, HW-SW) while achieving the high performance density (i.e. the performance per unit area per unit power) that is required for consumer systems.