The 8-bit Parallel CRC-32 Research and Implementation in USB 3.0
This thesis proposed 8-bit parallel CRC-32 in order to meet the high throughput of USB3.0. The highest speed of USB3.0 reaches 5G bps. Firstly, we researched the Data Packet structure and the principles of the CRC-32 in the USB3.0 Specification. Secondly, deduced the equation of the 8-bit input data and the CRC-32. Finally, implemented the CRC-32 coding and decoding by the verilog HDL, verified the correctness of the design. The 8-bit parallel CRC-32 can process 8 bits every clock cycle.