Silicon assembler design of a DCT/IDCT ASIC for real-time JPEG/MPEG compression
A single multiplier skewed pipeline architecture is presented for real time computation of the 1D discrete cosine transform (DCT)/IDCT in a 2- mu m process. This architecture is extended to the 2-D case using a single 1-D DCT module by an appropriate choice of algorithm. Silicon compilation techniques are used, and the design of three module generators is examined.<<ETX>>