A low phase noise frequency synthesizer for GPS RF receiver
In this paper, a low phase noise integer-N PLL has been implemented for GPS applications in a 0.13µm CMOS process. An integer-N PLL based frequency synthesizer is designed to generate differential local oscillator (LO) signals for down-converting the received GPS signals in L1 band to an intermediate frequency (IF) of 4.092MHz. For phase noise reduction, a robust structure of phase frequency detector and trimming LC VCO is proposed in this paper. The post-layout result achieves in-band phase noise of −95.4dBc/Hz@10kHz and out-band phase noise of −118.7dBc/Hz@1MHz. The receiver consumes 11.5-mW from a 1.2-V supply while the core of PLL occupying a 1.21-mm2 die area.