High-speed disturbance-free nonvolatile flip-flop based on complementary polarizers
This paper presents a hybrid CMOS/magnetic nonvolatile flip-flop (NVFF) for standby-power-critical and quick-startup applications. Different from conventional magnetic NVFFs, which are based on the two-terminal magnetic tunnel junction (MTJ), the proposed NVFF employs the complementary-polarizer magnetic tunnel junction (CPMTJ) to introduce the non-volatility. The writing and sensing circuits of CPMTJ are separately merged into the master stage of the NVFF to perform store and restore operations when the power turns on/off. In addition, the proposed NVFF is designed to operate as fast as the conventional CMOS flip-flop in the active mode. For performance evaluation of the proposed structure, SPICE model of CPMTJ is developed based on the theories of spin-transfer-torque (STT) switching and tunneling magnetoresistance effect, and then simulations are conducted in comparison of the conventional magnetic NVFF. Simulation results show that the proposed NVFF achieves 59% faster storing speed under iso-writing transistor width condition and 57% reduced storing energy for the same storing speed. By utilizing the cancellation of opposite spin-transfer torques, the proposed structure is expected to achieve a fully disturbance-free restore operation. Moreover, a 4GHz toggling speed in the active mode is demonstrated in SPICE pre-layout simulations using 45nm CMOS technology.