A high speed motion estimator using 2-D log search algorithm
Summary form only given. This paper describes the design of a high speed motion estimator using the 2-D log search algorithm. The architecture consists of 5 simple processing elements (PE) where each PE is capable of computing the sum-of-absolute-difference (SAD) to exploit the parallelism. For each step in the 2-D log search procedure, the 5 SADs of the 5 search points are computed in parallel. The design is implemented using Verilog and synthesized using Synopsys. Simulations show that the architecture is able to generate the motion vector for each 16/spl times/16 macroblock in 14.58 /spl mu/s for 3-step log search, and 24.30 /spl mu/s for 5-step log search. The architecture is thus well suited for encoding MPEG2 video up to MP@ML.