An 8-bit, 3.8GHz dynamic BiCMOS comparator for high-performance ADC
This paper deals with a monolithic dynamic voltage comparator with sampling speed up to 3.8GHz and a resolution of 8-bit. To improve the power-speed tradeoff, the front-end pre-amplifier is being designed with high f/sub T/ (80GHz) Si-SiGe heterojunction bipolar transistor (HBT) for higher speed while the dynamic latch along with the output buffer is implemented in 0.25/spl mu/m standard CMOS process to keep the power level low. To operate the CMOS latch at 3.8GHz sampling rate, a tailor made 3-/spl Phi/ clocking scheme is employed where the reset time of the latch falls up to 45ps in the reset mode. In the tracking mode, controlled decision transferring is done from pre-amplifier to the latch. At the latch output, a buffer with hysteresis is used to overcome the switching noise of latch and produce sharp, well defined digital data. The active power consumption by the core comparator is /spl sim/9mW and it takes a core area of /spl sim/0.017 mm/sup 2/.