A double regulated footer and header voltage technique for ultra-low power IoT SRAM
This work presents an ultra low power SRAM circuit which is suitable for tight power budget of IoT microcontrollers. The leakage power reduction technique using double regulated footer and header voltage in order to meet the requirements for retaining data SRAM in IoT applications. In normal SRAM operation, header and footer voltage are regulated full rail voltage by VDD and VSS, respectively. In idle mode, SRAM cell supply voltage should be lowered as much as possible to reduce more leakage current but still keep data without loss. Body effect is more efficient by lowering supply voltage on double header and footer than just only header or footer at same noise margin. By doing so, the author compares three techniques of the single regulated footer voltage (SRFV), single regulated header voltage (SRHV) and double regulated footer and header voltage (DRFHV) to make conclusion in term of power saving. In the fair comparison in active mode, author realizes that double regulated footer and header voltage technique is more efficiency power saving than three other techniques in retention mode.