Guest editorial - Special issue on neural networks hardware implementations
S INCE the very beginning of the neural network era, there has been the belief that to fully exploit the potential of this technology it would be necessary to also develop efficient hardware implementation techniques. In the last two decades, we have witnessed how the neural networks community is managing to acquire a more profound understanding of what neural networks can do and how. Neural networks knowledge has been enriched by developing more solid mathematical frameworks, by elaborating more efficient and powerful algorithms, by unfolding mysteries behind biological neural networks both at the individual neuron level and at different hierarchical levels of neuron ensembles and brain functions. In the last decade, we have seen how the initial " euphoria " of neural network expectations has settled down to a solid knowledge and research capable of undertaking complex problems and providing powerful solutions. In the field of hardware implementations , progress has been continuing as well. The challenge has been and still is to follow what biology does and how, to be able to build more complicated and larger size systems, to implement efficient hardware learning techniques, to improve speed and/or lower power consumptions, to efficiently exploit or develop new signal/state representation techniques (e.g., continuous time , pulse based, spiking nature, ...), to exploit noise and statistical properties, etc., and to apply all these ideas in real-world applications where efficient hardware solutions are necessary to provide compactness, high-speed and low-power consumptions. In recent years significant progress in hardware solutions is being achieved. For this reason we believe it is a good point in time for a Special Issue on Neural Networks Hardware Implementations for the IEEE TRANSACTIONS ON NEURAL NETWORKS. The Special Issue Call for Papers had an overwhelming response. Originally, 70 papers were considered for possible publication. From those, 35 made it finally into the Special Issue. The review process was carried out by splitting the load between the four guest editors. The review process went quite smoothly thanks to the close cooperation between guest editors and the fast efficient response of reviewers. The final set of papers can be grossly classified into two main groups of similar size: the mainly digital papers and the mainly analog papers. Within the analog group are included also the mixed Analog–Digital implementation papers. Besides this main classification the subsequent subgroups are many times fairly arbitrary, because most of the times the possible classifications …