An enhanced area-efficient on-chip compensation technique for power converters
A novel high area-efficient on-chip lag (PI) compensation technique for power converters is proposed in this paper. This technique combined current-mode with voltage-mode capacitor multiplier. The compensation capacitor can be reduced to smaller than 10% of the conventional one. This proposed technique is successfully verified by a boost converter system with current program mode (CPM) control. The system proves to be stable for loading conditions from 100mA to 300mA. While conventional compensation capacitor and resistor are 30pF and 2.5MΩ, the proposed technique needs only 3pF and 1.2MΩ consuming 8μA extra current.