A PVT-insensitive all digital CMOS time-to-digital converter based on looped delay-line with extension scheme
This paper presents a PVT-insensitive all digital CMOS time-to-digital converter (TDC). The proposed TDC uses hierarchical architecture including looped delay-line with extension scheme. The TDC is implemented and simulated in 0.18μm CMOS process. A calibration algorithm is proposed to make the TDC match all PVT conditions. It works with 48.98ps resolution under typical condition and the maximum measurement error is ±100ps under all PVT conditions.