A 10-bit 120-MS/s SAR ADC in 90nm CMOS with redundancy compensation
This paper proposes a single-channel 10-bit 120MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) in 90nm CMOS process with a 1.2-V supply voltage. By using a partial-monotonic switching sequences, the common-mode voltage variation is reduced efficiently. The binary redundancy compensation technique is adopted to solve comparator errors caused by dynamic offset and DAC settling. Compared to the conventional structure, the proposed method reduces the total capacitance by 4x, which enhances the speed and decreases the chip area. The simulation results indicate that the prototype achieves a SNDR of 60.27dB and an ENOB of 9.72b with a 58.134MHz input signal at 120MHz sampling rate, while only consuming 3.24mW power.