On gate leakage reduction in dynamic CMOS circuits
Scaling CMOS technology to next generation improves performance, increases transistor density, and reduces power dissipation per device. However, scaling also increases subthreshold and gate leakage currents, which greatly degrades circuit noise immunity and increases the chip total power dissipation. In this paper we propose a new leakage reduction circuit technique for domino dynamic CMOS circuits with no performance degradation and with minimal area overhead. Simulations show an 88% reduction in standby gate leakage using Berkeley predictive technology models (BPTM) of 65nm with no performance degradation over standard domino circuits. Simulations also show that the proposed technique is 17% more robust against loading variations compared to previously proposed leakage reduction techniques.