An enhanced low-power computational kernel for a pipelined multiplier-accumulator unit
A novel low power Computational Kernel (CK) for pipelined multiplier-accumulator unit is proposed. It is composed on of 1-bit full adder cell and a C/sup 2/MOS latch. This new CK offers efficient solutions to several problems experienced by existing cells such as large driving load, delay-time in the sum signal, unwanted transitions and the increase in the short circuit power component. Simulations of several prototypes have shown that the new CK consumes 18% less power than most of the other cells at several voltages. The MAC unit based on the new CK consumes 35% less power than the standard MAC units and can also operate efficiently at lower voltage.