Performance evaluation of 1-bit CMOS adder cells
Evaluating the performance measures of a full adder cell, like other circuits, is input pattern dependent. The issue gets more complicated when evaluating several parameters such as time delay, area, power dissipation, and correct functionality at the same time. The proposed input test pattern is based on full coverage of all possible transitions from one input pattern to another. It is composed of two parts: the first is a 56 transitions input pattern for speed measurement, followed by 9 different input patterns concatenated together for power consumption measurement. The proposed input test pattern proves the correct functionality, and produces correct time delay and power dissipation. Using this input test pattern guarantees correct and fair comparison among different full adder cells.