Hardware verification using symbolic state transition graphs
A new approach for hardware verification using symbolic state transition graphs (implemented in BDDs) is presented. We propose a novel idea, a symbolic state transition graph (STG), which can represent finite state machines FSM in terms of the relations between symbolic input variables, state variables, and output results, rather than the exact input-output bit patterns. Compared to conventional STG methods, the symbolic STG is more concise, higher-level, has fewer states and is easier to specify. Based on the transition relation method and an event-driven scheduling technique to compute the symbolic states, we propose two algorithms to verify the circuit implementation with respect to its symbolic STGs. The algorithms can be used to find out a necessary condition for the implementation to satisfy the specification, which can be used for the allocation of design errors.<<ETX>>