A Nondestructive Method of Extracting the Width and Thickness of Interconnects for a 40-nm Technology
In this paper, a simple and nondestructive method of modeling 40-nm interconnects is proposed. Traditional methods based on charge-based capacitance measurement model the interconnects by fitting the capacitance or resistance curves, first by assuming one constant process parameter, such as metal thickness, and then by extracting the metal width, metal spacing, and interlevel dielectric (ILD) thickness from certain test patterns that may therefore result in model inaccuracy while the transmission and scanning electron microscopy methods are both destructive and time consuming. The proposed new methodology directly extracts the metal width based on the metal resistance test structures, and then the metal thickness, metal spacing, and ILD thickness without any presumption. It is also nondestructive and fast, with a model accuracy higher than 95%. Furthermore, with the ensured accuracy of layout parameter extraction, the necessity of an accurate interconnect model in the 40 nm technology and beyond is emphasized.