VLSI Implementation of a Selective Median Filter
0001 0 0 1 0 0011 0111 1001 In this paper, the VLSI implementation of a selective median filter for the real-time applications is presented. T h e proposed design is based on a novel bit-level running algorithm with a modular and parallel in structure. A chip designed by the cell-based style is demonstrated to show the hardware realization. The performance of the proposed design is also presented.