Off state incorporation into the 3 energy mode device lifetime modeling for advanced 40nm CMOS node
Hot-Carrier degradation is analyzed with 3 mode lifetime modeling extended to the cases of PMOSFETs and Off state modes in last CMOS nodes. Damage worsens in subthreshold region with positive temperature activation due to interface traps generation in the gate-drain overlap (GDO) and localized charge trapping into the spacer oxide. Care has been done on the distinct impact of the measuring bias and stressing conditions in Sub-VT regime. The latter can be much more degraded than On-state parameters showing the amphoteric nature of Si-H bonds breaking rates throughout the channel-GDO. Off-mode damage has been included in the 3 mode energy device lifetime giving a useful modeling for any AC waveforms suitable for digital to analog operations.