A 60GHz quadrature LO synthesizer with 1.2° phase error and over 17% tuning range for IEEE 802.11ad applications
This paper proposes a 60GHz quadrature LO synthesizer with wide tuning range and low phase noise performance. The synthesizer is implemented by a 20GHz quadrature PLL and a 60GHz wideband tripler. The 20GHz PLL achieves an excellent phase noise performance of -107dBc/Hz@1MHz offset while showing a tuning range of over 17%. A 4-bit switched capacitor array is used to cover the four prescribed channels of the IEEE 802.11ad standard. The proposed 60GHz tripler mixes the fundamental frequency and second-order harmonic of the 20GHz PLL output. The total phase noise is -95dBc/Hz@1MHz offset at 60GHz. A buffer is used to drive the 50Ω load off-chip, achieving a 0dBm output power. The LO synthesizer is designed by 90nm CMOS process with 1.2V supply. The total power consumption of the PLL is 39mW while the tripler only consumes 12.6mW.