A new cell for low power adders
Reducing power dissipation at the circuit level is considered one of the main factors in developing low power systems. Also, minimizing power of the most commonly used circuit module, will lead to a global power reduction. Following these two design philosophies, a low power speed adder has been developed based on a new cell. This cell is a combination of an XOR gate and transmission gate. It offers both low power and high speed performance. The proposed cell has been compared with two other basic common cells. An extensive analysis of three types of adders, namely carry lookahead, carry select and carry skip has proved the superiority of the proposed cell.