Ruggedness Characterization of Bonding Wire Arrays in LDMOSFET-Based Power Amplifiers
Electro-thermo-stress (ETS) failure of bonding wire array in a laterally diffused metal oxide semiconductor (LDMOS) field-effect transistor (FET)-based power amplifier during its high power’s ruggedness experiment is investigated in this paper. A special measurement system is at first set up to get reliability of the bonding wire array, where a microscope is used to capture its fractures. The temperature distribution of the LDMOSFET die surface and bonding wire array is also captured by a thermal infrared scanner to investigate the principle underlying the failure of ETS fractures. Simulation studies are also performed. The temperature distribution is closely related to the profiles of the bonding wire array. Numerical methods are employed to calculate the bonding wire array, and the temperature distributions are demonstrated by using our finite-element method code. It also works well in solving the transient temperature of the bond wire array with the stationary current and the heat source from the silicon region. The simulated thermal results agree well with the testing results. Finally, an improved LDMOS design in optimizing the bonding wire profile is proposed. This research can serve as a guide for the design of an LDMOS PA with enhanced reliability.