An efficient approach to improve PSRR performance of Kuijk BGR topology
A highly efficient approach to improve PSRR behavior of Kuijk BGR topology is derived though small signal transfer function analysis and, a BGR circuit has been designed and fabricated on standard 0.5μm CMOS technology to verify this method. This thought greatly relieves the trade-offs of BGR circuit design among power consumption, PSRR performance, area and etc. This BGR circuit consumes 3μA current at 5V single power supply, with >130 dB DC PSRR performance, occupies an area of 350μm×100μm, and is of self-biased characteristic with 2~6 V work supply voltage range.