A low power VLSI design paradigm for iterative decoders
In this paper we present low power maximum a posteriori (MAP) decoder architectures using dual supply voltages. The architecture leverages an application specific integrated circuits (ASIC) structure, where the architecture components that require a higher performance are powered from a high supply voltages V/sub ddH/, and the less demanding components are powered from a low supply voltage V/sub ddL/. Salient features of this architecture include: (a) high level of parallelism, (b) reduced power consumption without affecting the architecture performance, and (c) a tradeoff between the decoding time delay and the number of state metric banks, branch metric banks, and state metric update kernels respectively. The power consumption reduction of the dual-supply voltage over the single-supply voltage has been estimated and the memory access frequencies as well. The proposed architecture achieves approximate 35-40% power reduction from the single-supply architecture.