Low complexity decimation filter for multi-standard digital receivers
This paper proposes a reduction in complexity of decimation filter architectures used in multi-standard digital receivers, using IIR filters implemented as a sum of two all-pass filters. The decimation filter is an important block in devices which want to establish communication using different standards. IIR filters are implemented on specific stages of multistage pipeline/interleaving structures, where high order filters are power consuming and area demanding. Therefore, a major reduction in complexity is obtained. Regularity is an important property of all-pass filters, which can be decomposed on first or second order all-pass transfer functions achieving more efficient implementation. The results presented are implemented in pipeline/interleaving architectures using specific decimation decomposition proposed previously. Reductions of 36%, 77%, and 80% are obtained compared with previous works, where basically these implementations are based on linear phase filters. The decimation filter architecture is simulated using Matlab.