Design and Implementation Of Word-Level Embedded Block Coding Architecture in JPEG 2000 Decoder
This paper presents a word-level decoding architecture of embedded block coding (EBC) in JPEG 2000. This architecture decodes one coefficient per cycle based on the proposed word-level decoding algorithm. This algorithm eliminates state variable memories by decoding all bit-planes in parallel. The proposed column-switching scan order overcomes intra bit-plane dependency and inter bit-plane dependency to enable parallel processing. Implementation results show the proposed architecture can decode 54 MSamples/s at 54 MHz, which can support HDTV 720 p (1280times720, 4:2:2) decoding at 30 frames/sec in real time