Cable-Geometric Error-Prone Approach for Low-Latency Interconnection Networks
Interconnection network is a main concern in the architecture design of highly parallel systems such as high density data centers and supercomputers that reach millions of endpoints, e.g., 10M cores for Sunway TaihuLight system. As the number of endpoints of such systems has gradually increased to meet the higher computing and storage demand, the interconnection network is required to provide a low latency and high communication bandwidth, i.e., less than 1-microsecond latency across systems with a link bandwidth is greater than 100GB/s. In the low-latency design context, our primary aim is to provide a novel solution based on the technology-driven approaches: (1) cable-geometric small-world network topology with custom routing, and (2) the use of an FEC(forward error correction)-free error-prone mechanism for a high-speed low-reliable link. Both can present a logarithmic diameter low-radix network with low-latency and high-bandwidth switches, although approximate computing or ABFT (algorithm-based fault tolerance) design is required for parallel applications.