Rate-optimal static scheduling for DSP data flow graphs onto multiprocessors
This paper is concerned with finding a rate-optimal compile-time (static) scheduling of data flow graphs (DFGs) onto multiprocessor systems. A new analytical approach is proposed to produce a rate-optimal time schedule for a fully specified DFG. In this approach, the DFG is transformed into an acyclic graph through a sequence of circuit contractions. An algorithm to contract a circuit as well as an algorithm to achieve a time scheduling of the given DFG are given. In the scheduling algorithm, the resulting acyclic graph is scheduled followed by a scheduling of the circuits in an order which is reverse to that of their contraction. Further, the issues related to optimizing the schedule in terms of the I/O delay and the number of processors needed, are addressed.