A 160 MSPS 8-bit pipeline based ADC
This paper presents an 8-bit 160-MS/s pipeline analog-to-digital converter using 0.25-micrometer double poly BiCMOS technology of which the total power dissipation is 135mW with 3.3V of analog power supply. The input signal is assumed to be IV. Double sampling technique is used to increase the sampling speed. The sub-circuits are optimized in terms of power and speed. It achieves differential nonlinearity and integral nonlinearity of /spl plusmn/0.65 LSB and /spl plusmn/0.8 LSB and an estimated area of 1.60mm/sup 2/.