Three-dimensional defect sensitivity modeling for open circuits in ULSI structures
In the last three decades, device feature size has been reduced from ten's of microns to sub-0.5 /spl mu/m, shaping what is commonly called the ultra large scale integration (ULSI) era. At the same time, there has also been an appreciable decrease in the defect density over these years. While some of the defects have been completely eliminated, many still remain in modem fab lines. In view of the continuing trend of feature size reduction, the three-dimensional (3-D) nature of these defects is likely to have an impact on the functionality of integrated circuit (IC) structures. An open circuit is conventionally modeled as a break in a conductor due to an insulating defect. For 3-D defects and conductors, this physical interpretation of open circuits may not be the most appropriate one. In this paper, we present a parametrized modeling of open circuits for 3-D defects in ULSI processing. In the proposed approach, the maximum allowable increase in a conductor's resistance due to a partially or completely embedded insulating defect is suggested as the criterion for an open circuit. Analytical expressions for ULSI defect sensitivity are then obtained.