High speed and high throughput 8×8 bit multiplier using a Shannon-based adder cell
The adder circuit is used as a main component in the multiplier circuits. The Baugh-Wooley, Braun and CSA multipliers are designed by using our proposed adder cell. The proposed adder circuit is designed by using Shannon theorem. The multiplier circuits are schematised by using DSCH2 VLSI CAD tool and their layouts are generated by using Microwind 3 VLSI CAD tool. The proposed adder based multiplier circuits are simulated and results are compared with MCIT and CPL based adder cell in terms of power, area, delay, EPI, Throughput, and Latency. The proposed adder based multiplier circuits are simulated by using 90nm feature size and corresponding supply voltage 1V. The Shannon full adder circuit based multiplier circuits gives better performance than other published results in terms of power dissipation, propagation delay, throughput and latency due to less number of transistor used in Shannon adder circuit. Since the maximum drain current is also not increasing significantly with temperature in our multiplier circuits, therefore, power dissipation of the circuit is less.