Display Verification IP Core Design Based on Star-Extraction and Star-Recognition Image Processing on FPGA
This paper presents FPGA based VGA display interface design for image display verification during test procedure in the star sensor debugging phase. Methods of asynchronous FIFO, methods for data update during line blanking interval and vertical blanking interval were adopted, and CCD camera's requirements for special sequential order were satisfied, and the metastable state problem caused by data's cross clock domain were solved. Experiment results show that the system provides effective verification platform for ground function test of star sensor.