An efficient parallel execution for intra prediction in HEVC Video Encoder
An efficient parallel execution of High-Efficiency Video Coding (HEVC) intra prediction is proposed. The proposed parallel block based frame interleaving technique can remove the data dependency in the intra 4×4 blocks and improve the parallel processing between them. Therefore, the timing constraint of real-time 4kx2k encoding can be achieved. Prediction engines of various sizes: 4×4, 8×8, 16×16, 32×32 and 64×64, work in parallel to enhance the throughput with high hardware utilization. The hardware size of the proposed architecture is 1,524k gates. Experimental results show that the maximum throughput reaches 265Mpixels/s with operating frequency of 146 Mhz. The proposed architecture can compute 4096×2160p video at 30fps.