A power and area efficient CMOS charge-pump phase-locked loop
In this paper, a power and area efficient charge-pump phase-locked loop (CPPLL) is proposed. The design utilizes a top-down methodology to determine system parameters. The PLL is implemented in 0.18μm CMOS technology and its supply voltage is 1.8V. The PLL has in input clock frequency of 25MHz and an output clock frequency of 0.8-1.6GHz with 50μm*110μmactive area. Measurement results show that the PLL without output buffers consumes 11.7mW and the root-mean-square jitter of the VCO at 1.6GHz is 7.37ps.