A Novel LMS-Based Calibration Scheme for Fractional-N Digital PLLs
In today's fractional-N phase-locked loops, digital-to-time converters are commonly used to cancel the quantization noise of the divider modulus, and a least-mean squares loop is used to adapt the gain of the cancellation path. Unfortunately, a trade-off exists between the time range needed to the digital-to-time converter and the speed of convergence of the calibration. In this paper, a novel scheme significantly relaxing this trade-off and allowing for a low-power implementation of both the digital-to-time converter and the calibration loop, is introduced. The effectiveness of the proposed concept is verified via behavioral simulations in the presence of circuits non-idealities, showing a reduction of at a least a factor of 5× in the settling time of the calibrated coefficient.