A cost effective reconfigurable memory for multimedia multithreading streaming architecture
Data flow plays an important factor when design a multimedia multithreading streaming system. In this paper, a reconfigurable memory architecture is proposed to smooth the stream data flow to decrease maximum stream data bandwidth from the external memory. The reconfigurable memory not only can configure as data cache but also can configure as tightly couple memory depending on the application. In addition, heterogenous threads level configurability can adjust the optima on chip thread number in different pipeline stage. Experiment shows the proposed architecture can reduce at least 27% external bandwidth and increase at least 25% throughput in a graphic streaming example.