Improved Characterization Methodology of Gate-Bulk Leakage and Capacitance for Ultrathin Oxide Partially Depleted SOI Floating-Body CMOS
Device scaling of partially depleted (PD) silicon-on-insulator (SOI) has the potential to increase speed. However, the increased gate tunneling and capacitance will complicate device behaviors and increase the difficulty in characterization for modeling purpose. For the first time, gate-bulk leakage current <i>I</i><sub>gb</sub> and gate capacitance <i>C</i><sub>gg</sub> characterization methodology for PD SOI floating-body (FB) CMOS with high accuracy is proposed and verified in 40-nm SOI devices. These devices are with ultrathin equivalent oxide thickness of 12Å, and radio frequency-capacitance voltage (RF-CV) technique is used for <i>C</i><sub>gg</sub> measurement to overcome the impact of leaky gate current. This methodology can eliminate properly the parasitic elements due to the coexistence of opposite poly gate type in the SOI T-shape body-tied device and accurately characterize and model <i>I</i><sub>gb</sub> and <i>C</i><sub>gg</sub> behaviors for the PD SOI FB devices. Test patterns are designed with RF ground-signal-ground configuration and same test patterns can be used for both <i>I</i><sub>gb</sub> and <i>C</i><sub>gg</sub> characterization. Impact of <i>I</i><sub>gb</sub> and <i>C</i><sub>gg</sub> changes on the history effect, and speed and body potential is analyzed by BSIMSOI4.0 models. Simulation accuracy of history effect will have at least 3% improvement with this proposed methodology.