Low Power Design of Double-Edge Triggered Flip-Flop by Reducing the Number of Clocked Transistors
In this paper, a new technique for implementing low energy double-edge triggered flip-flops is introduced. The new technique employs a clock branch shared (CBS) scheme to reduce the number of clocked transistors in the design. As compared to the other state of the art double-edge triggered flip- flop designs, the newly proposed CBSip design has an improvement of up to 20% and 12.4% in view of power consumption and PDP, respectively.