Low power/high speed design of a Reed Solomon decoder
With the spread of Reed Solomon codes to portable applications, low power RS decoder design has become important. This paper discusses how the Berlekamp Massey Decoding algorithm can be modified in order to obtain a low power architecture. In addition, modifications that speed-up the syndrome and error computations are sugested. Then the VLSI design of a low power/high speed decoder is described. The power reduction when compared to the normal design is estimated.