Parallel implementation of a cut and paste maze routing algorithm
Wire routing is a compute bound phase in the design of VLSI circuits. Some of the software solutions to this problem entail divide and conquer methods, such as hierarchical routing, in order to reduce its time complexity. Hardware accelerators have been employed to achieve further increase in the speed of this process. Implementation aspects of a reduced array architecture (RAA) for hardware acceleration of the cut and paste hierarchical routing algorithm are detailed. Several macros are defined to implement the algorithm in hardware. The architecture is implemented in double-metal 2-/spl mu/ CMOS technology.<<ETX>>