Timing jitter and bit errors in a 64-bit circular shift register
The bit-error rate of a 64-bit single-flux-quantum circular shift register, operating at a clock frequency of 10-16 GHz was measured. Error incidence depends on the values of the clock and data bias currents and on the clock frequency. Timing violation arising from thermal jitter is the dominant error mechanism. The jitter per JTL stage is estimated to be 290 fs based on the error rate data. This corresponds to a noise temperature of 8-9 K.