Device and Circuit Interaction Analysis of Stochastic Behaviors in Cross-Point RRAM Arrays
Stochastic behaviors of resistive random access memory (RRAM) play an important role in the design of cross-point memory arrays. A Monte Carlo (MC) compact model of oxide RRAM is developed and calibrated with experiments on various device stack configurations. With MC SPICE simulations, we show that an increase in array size and interconnect wire resistance will statistically deteriorate write functionality. Write failure probability (WFP) has an exponential dependence on device uniformity and supply voltage <inline-formula> <tex-math notation="LaTeX">$({V}_{\textsf {DD}})$ </tex-math></inline-formula>, and the array bias scheme is a key knob. Lowering array <inline-formula> <tex-math notation="LaTeX">${V}_{\textsf {DD}}$ </tex-math></inline-formula> leads to higher effective energy consumption (EEC) due to the increase in WFP when the variation statistics are included in the analysis. Random access simulations indicate that data sparsity statistically benefit write functionality and energy consumption. Finally, we show that a pseudo-subarray topology with uniformly distributed preforming cells in the pristine high-resistance state is able to reduce both WFP and EEC, enabling higher net capacity for memory circuits due to improved variation tolerance.