FPGA architecture of HMM-based decoder module in speech recognizer
This paper presents the reconfigurable architecture and implementation of HMM-based decoder module in speech recognizer on FPGA. The architecture is done with different parameters of speech recognition system that could be easily reconfigurable. The design and implementation on FPGA have been verified with utterances of 800 test speeches. The implementation results, the recognition accuracy results of up to 98% are also presented.