Hardware architecture design of video compression for multimedia communication systems
VLSI realization of video compression is the key to many real-time multimedia communications systems. Among the video compression algorithms, the newly established MPEG-4 and, in particular, H.264 standards have become increasingly popular. However, the high coding efficiency of such video coding algorithms comes at the cost of a dramatic increase in complexity. Effective and efficient hardware solutions to this problem are necessary. In this article we present an overview of the hardware design issues of MPEG-4 and H.264. Both module and system architectures of these two coding standards are discussed. Based on these architectures, the design of a single-chip encoder complying with the H.264 baseline profile and capable of encoding the D1 resolution (720 x 480) video at 30 Hz is presented as an example. In addition, the system integration issues of video compression engines with multimedia communication systems and a general hardware platform for various applications are discussed.