Effect of dielectric engineering on analog and linearity performance of gate electrode workfunction engineered (GEWE) silicon nanowire MOSFET
This work demonstrates that with the incorporation of gate stack (GS) on GEWE-SiNW MOSFET, the analog and linearity performance of the device enhances in terms of transconductance, output conductance and device efficiency. The important Linearity figure of merits (FOMs) such as second order voltage intercept point (VIP2), third order voltage intercept point (VIP3), third order input intercept point (IIP3), third order intermodulation distortion (IMD3) and 1-dB compression point are studied with the help of 3D ATLAS and DEVEDIT device simulator for low power linear CMOS devices. Moreover, it has been observed that the zero-cross over point for GS-GEWE-SiNW MOSFET is reduced appreciably compared to its counterparts, which results into lowered optimum bias point for device operation.