A new simultaneous partitioning and chip placement approach based on simulated annealing
A major issue in VLSI design is that of determining how circuit components are to be distributed among a set of chips (partitioning problem) and where these chips are to be located on a board (placement problem) in order that densely connected components are placed close together and the wiring between the chips is minimized. A new partitioning and placement approach is proposed in which these problems are solved simultaneously rather than independently. A framework for annealing has been developed and cost models that allow the desired results to be achieved have been derived. It is shown experimentally that the approach results in easily routable designs.<<ETX>>