Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing
This paper studies the problems of minimizing power dissipation of an interconnect wire by simultaneously considering buffer insertion/sizing and wire sizing (BISWS). We consider two cases, namely minimizing power dissipation with optimal delay constraints, and minimizing power dissipation with a given delay penalty. We derive closed form optimal solutions for both cases. These closed form solutions can be used to efficiently estimate the power dissipation in the early stages of the VLSI designs. We observe that the power dissipation can be much different even with the same optimal delay.