A building block chip for a scaleable ATM architecture
In this paper, a building block chip for a scaleable ATM switch architecture is developed. The architecture is based on a modified banyan interconnection network of this chip. Crossbar technology is employed for the switch chip. A prototype of the switch chip is implemented in Dynamic/Static/C/sup 2/MOS 2.0 micron technology using the Cadence tools environment. The performance of the chip has been optimized using a full custom design approach and a mix of technologies. The developed prototype supports a data rate of 155.52 Mb/s with a high speed of 155.52 MHz using serial inputs and outputs, and a lower speed of 38.88 MHz using four bit wide parallel inputs and outputs. The developed system and chip are fully scaleable up to a size of 256 by 256 channels, which could easily be extended in future versions.