A novel approach for leakage power reduction in deep submicron technologies in CMOS VLSI circuits
Leakage currents are one of the major design concerns in Deep sub-micron (DSM) technology due to rapid integration of semiconductor industries by reducing the transistor size. Many parameter has been reduces with technology scaling such as Threshold voltage, oxide thickness, channel length and supply voltage (Vdd) has been reduced to keep power consumption under control. As a consequence, the transistor threshold voltage (Vth) is also scaled down to maintain the drive current capability and to achieve performance improvement when reducing the technology node. However, the threshold voltage reduction increases sub-threshold current exponentially. In this paper analysis of some of the leakage reduction technique and compare them with proposed technique for mitigating the leakage power, with the combination of sleep with Galeor which reduces the average power consumption for low and High Vth in Basic Nand Gate 36.47% & 49.0%, Force Stack 62.90% & 70.18%, Sleep Transistor with Low Vth 33.30% & 46.39%, High Vth 47.66 % & 57.93%, sleepy Keeper 58.92% & 66.98 % respectively.