CRG Godel Based High-level Test Generation algorithm for VLSI
The development of IC technique, makes IC test to become more and more difficult, and the test expenses has been taken higher proportion in total cost of the IC product, the test expenses even may go higher than the manufacturing cost. Existed high-level circuit models usually can not behave well to demonstrate the controllability, the observability, and the sequence information. Aimed at settle this common problem, a new CRG circuit model was abstracted in this paper. The model is based on the widely adopted techniques in the circuit design, the register transfer level (RTL) behavioral descriptions. The model has the capacity to show the circuit control manner and the data relationships. And on the base of this circuit model, directly test generation method or testability analysis method was proposed. The experimental result indicated that, the proposed model and corresponding algorithm are effective, and the generating test sequence can be used not only in design confirmations or chip test, but also have ability for helping testability analysis for high level description.