Optimal monobit digital receiver for QPSK modulation with phase rotation
High-speed high-resolution analog-to-digital converter (ADC) is a key bottleneck in large-bandwidth systems such as 60 GHz communication of wireless personal area networks (WPANs), due to its large power consumption and high complexity. Hence, monobit ADC has been previously proposed to address this problem. In this paper, we propose a receiver architecture with monobit sampling and carrier phase rotation for quadrature-phase-shift-keying (QPSK) modulation. The optimal rotation phase is derived from the achievable-rate point of view. Then, a suboptimal but low-complexity monobit receiver is obtained, and the impact of different rotation phases is investigated. The optimal rotation phase is found to be π/4. Simulation results show that there is only about 1dB signal-to-noise ratio (SNR) loss with a rotation phase deviation of 15° from the optimal value, providing a pretty good robustness to implementation imperfection.