An oversampling digital pixel sensor with a charge transfer DAC employing parasitic capacitances
An image sensor design with pixel-level sigma-delta (ΣΔ) conversion employing four transistors at each pixel where the feedback charge transfer is realized through the parasitic capacitances of an inactive transistor is presented. This architecture is a relatively simple and robust design where the only analog components required outside of the pixel array are shared row comparators and a voltage mode digital-to-analog converter (DAC) to supply the in-pixel charge feedback structures. The photodiode acts as the integrator of the ΣΔ modulator and an in-pixel charge feedback DAC is realized with two PMOS transistors. A third, minimum size PMOS transistor operating in the cut-off region provides capacitive coupling through which a controlled amount of charge is injected to the photodiode. The sensitivity of the image sensor is determined by the size of the feedback charge packets in the ΣΔ modulator. The remainder of the image sensor is all digital, including a decimation filter to convert each pixel's single bit output stream into a multi-bit sample. We fabricated a test pixel structure in the TSMC-0.35µm CMOS technology with 10µm × 10µm pixels and a fill factor of 31%. Experimental results demonstrated a SNR of 60dB and a dynamic range of 83dB.