Application of thermal test chips to stacked chip packages
Thermal metrics for single-chip packaged semiconductors have been defined with respect to junction temperature and a thermal reference. The methodologies include thermal resistance analysis in varying degrees of accuracy. The single-value metric of θjx [1,2,3], or thermal resistance defined as the temperature difference from a semiconductor junction (j) to some specified reference (x) divided by the heat flux through the path (Eq. 1), is used extensively to evaluate the thermal performance of a given device. Simply put, the maximum junction temperature is measured or modeled and this value is used to determine if the product needs heat removal beyond the package and intended end-use application board. As integrated circuit feature size decreases the use of single-value metrics often times may not fully solve the maximum temperature problem or the cooling solution may be over- or under designed. The compact model [4,5,6,7] is a further refinement of the thermal resistance analysis method which uses multiple resistances to produce a boundary condition independent model. This method allows a more detailed analysis of complex thermal interactions within the package or system model which generally only describes one heat source, but may be extended to multiple chips or heat sources and suggest one possible solution [8].