Hot-Carrier acceleration factors for low power management in DC-AC stressed 40nm NMOS node at high temperature
Channel Hot-Carrier degradation presents a renewed interest in the last NMOS nodes where the device reliability of bulk silicon (core) 40nm and Input/Output (IO) device is difficult to achieve at high temperature as a function of supply voltage VDD and back bias V<inf>BS</inf>. A three mode interface trap generation is proposed based on the energy acquisition involved in distinct interactions in all the V<inf>GS</inf>, V<inf>DS</inf> (V<inf>BS</inf>) conditions as a single I<inf>DS</inf> lifetime dependence is observed with V<inf>GD</inf> > 0. This gives a new age(t) function useful for accurate DC to AC transfers. Positive temperature activation is explained by the rise of ionization rate with electron-electron scattering (medium I<inf>DS</inf>) and multi vibrational excitation (higher I<inf>DS</inf>) which increase the H desorption by thermal emission. The use of forward VBS has shown no gain under CHC for both device types. The main limitation occurs under reverse V<inf>BS</inf> = −V<inf>DD</inf> in IO where the smaller temperature activation partially compensates the larger damage. In that case a security margin can be established giving a limit of V<inf>BS</inf> = −V<inf>DD</inf>/2 for design reliability.