A novel reconfigurable on-board computer based on soft core CPU
To address the issues of single event upsets caused by radiation in outer space to micro-satellites, we proposed a novel reconfigurable on-board computer system with three soft core CPUs inside the Field Programmable Gate Array(FPGA), with the function of error detecting and restoring configuration. Two of the soft core CPUs act as the central processing unit, doing housekeeping of the satellite; and the third one includes a 32-bit floating-point mathematical co-processor core using the Coordinate Rotation Digital Computer(CORDIC) algorithm, dealing with complex mathematical operation. When SEU happens to our system, the system can detect it and send a message to trigger the restoring configuration. To verify our design, a semi-physical simulation platform consisting of the reconfigurable on-board computer, dSPACE simulating computer and laboratory display terminal is built, and capability of our design is proved on this platform. In the experiment, we inject errors artificially, and the errors can be detected and corrected by reconfiguring the whole system; when no errors are injected, the computer can take control of the satellite normally.