A lithography independent gate definition technology for fabricating sub-100 nm devices
In this paper, a lithography independent gate definition technology to fabricate sub-100 nm device is proposed and experimentally demonstrated. In the proposed technology, the device gate is formed by a spacer over a step next to the gate region. The gate height is thus determined by the step height and the channel is defined by the spacer width. Thus, the channel length is defined by the polysilicon layer thickness, which can be precisely controlled. Experimental results reveal that the resulting gate length is about 75-85% of the deposited film thickness. SEM photographs show that sub-50 nm lines can be formed using this method. Transistors fabricated using the new method have been characterized and excellent I-V characteristics are demonstrated.