Quantization Noise Suppression in Fractional-$N$ PLLs Utilizing Glitch-Free Phase Switching Multi-Modulus Frequency Divider
A novel programmable frequency divider for quantization noise (QN) suppression in fractional-N phase-locked loops (PLLs) is presented in this paper. The proposed phase switching multi-modulus frequency divider (PS-MMFD) utilizes a novel glitch-free phase switching (PS) divide-by-0.5/1/1.5/2 cell to reduce the frequency division step to 0.5 and its QN induced by ΔΣ modulation is thus suppressed by additional 6 dB. Compared with other frequency dividers used for QN suppression, the proposed glitch-free PS-MMFD is more robust, can operate at higher input frequency and consumes less power. Detailed analysis and implementation of the proposed glitch-free PS-MMFD is demonstrated, followed by experimental results from a fully integrated ΔΣ fractional-N PLL utilizing the proposed QN suppression technique. Implemented in a 0.18 μm CMOS process, the proposed glitch-free PS-MMFD occupies an area of 0.38 mm × 0.25 mm and consumes 5 mA from a 1.8-V supply at an input frequency of 2 GHz. Measurement results also demonstrate the additional 6-dB QN suppression by the proposed technique.