A multi-GHz area-efficient comparator with dynamic offset cancellation
In this paper we propose a dynamic impedance modulation technique to significantly improve the speed of comparators utilizing dynamic-offset-cancellation (DOC). Measurements from a 65nm test-chip show that DOC comparators utilizing the proposed technique achieve 6X lower input-referred offset and 9X better power supply noise rejection than a traditional StrongArm comparator with only a 20% speed penalty at identical core comparator area (98µm2) while dissipating 455µW.