RF characterization of Through Silicon Via test structures in a 3-tier stacked wafer
Experimental RF characterization of 3D interconnects in multiple stacked wafers is presented in this study aiming to validate models of 3D interconnect components that are required for the eventual realization of a 3D heterogeneous system. TSV structures in this study were fabricated using a via middle 3D IC fabrication process at CNSE's 300mm Si wafer prototyping facility. Series of 2-tier and 3-tier test structures were fabricated using a die to wafer Cu-Cu bonding process. The feasibility of manufacturing 3D IC interconnects in multiple stacked wafers for RF applications was verified and exhibited good reproducibility and DC characteristics. We investigated the substantial impact of substrate conductivity on high frequency signal transmission in 3D communication channels. Analysis of differences between various configurations in 2-tier and 3-tier test structures provides an approach for extracting RF characteristics for isolated TSV, RDL and bond pad modules. These results will provide important design guidance for high speed 3D interconnects in multi-tier stacked wafer systems.