Analysis of Clock Scheduling in Frequency Domain for Digital Switching Noise Suppressions
This paper presents a methodology for digital switching noise suppressions on the power lines at a fundamental frequency as well as its harmonics by using a clock scheduling technique in the frequency domain. Our approach provides a deep insight of the clock scheduling at the arbitrary phase shifts of clock signals. Moreover, an optimization algorithm is applied to find an optimal phase shift of a clock signal in order to maximize noise suppressions at a specific frequency band. The experimental results on a Xilinx field-programmable gate array Spartan-3 (XC3S400-TQ144) show that the estimated noise reduction rates well-match the measured ones. In these tests, dummy logics are used as noise injectors. This paper also presents a design example with a data encryption standard cryptoprocessor to demonstrate the applicability of our approach. The experiments show that the highest error between the estimated and the measured results is about 2.5 dB. Interestingly, our approach seems to be appropriately used with the designs in wireless communications where designers address to minimize the digital switching noise at the specific frequency bands of interest.