A 768 Megapixels/sec inverse transform with hybrid architecture for multi-standard decoder
This article introduces a fast hybrid architecture to perform the inverse transform for multiple standards including H.264/AVC, VC-1, MPEG-4, MPEG-2, H.263, and AVS. Both separated and common circuits are used in the hybrid architecture to get high throughput (768 Mpixel/sec for 8-point IDCT and 1536 Mpixel/sec for 4-point IDCT) while keep the area acceptable for many supported standards (56,989 logic gates @ 384 MHz). This hybrid architecture is also very expandable for future codec implementation. The design is described at RTL and synthesized using 130 nm cell library.