A novel high write speed, low power, read-SNM-free 6T SRAM cell
In the nano-scaled technologies, increasing sub-threshold leakage, dynamic power and degrading SNM pose major hurdle for future generation circuits, especially in SRAM arrays. In this paper, a novel high write speed, low power, read-SNM-free 6T SRAM cell is presented. Simulation using 128 times 16 SRAM array in 90 nm CMOS technology shows that the cell can achieve 64% faster write operation than the conventional cell. Experimental results show that the write and read energy of the proposed cell are 76.8% and 53% lesser than the conventional cell respectively. Write precharge energy for the proposed cell is almost 81% less than that of conventional cell. During read operation, the proposed cell does not induce any noise at data nodes (dasiaQpsila & dasiaQbarpsila) which makes it a read-SNM-free design.