Dopant and carrier profiling for 3D-device architectures
For continued downscaling at 22nm node and beyond, FinFETs have now emerged as the device of choice due to an unprecedented combination of performance improvement (increased Id) and power reduction (low leakage) [1]. A crucial aspect in the process design is the recognition that the drive current control in FinFETs is dominated by the sidewall doping (dose retention/activation), as shown in Figure 1 [2], whereas short channel effects are linked to dopant conformality. This represents a challenge for the junction formation of 3D-device architectures (FinFETs) as we need to combine both aspects simultaneously i.e. high sidewall doping and conformality. To achieve this goal several doping alternatives are being considered such as traditional ion implantation [3], vapor phase doping [4] and variants of plasma doping [5], [6]. Obviously, adequate development of these processes requires the availability of 3D-dopant and carrier profiling techniques with sub-nm resolution.