Design and VLSI implementation of MPEG audio decoder
The paper presents a chip design for an MPEG audio decoder, with a new modified scheme. In the modified decoding scheme, the required computations can be reduced to half of the original number, and the storage demand reduced too, i.e., the pseudo-QMF, a polyphase filter bank, only requires 512 words of memory for 1024 points. The major operators include one adder-subtractor and one multiplier-accumulator. The chip is achieved by using a silicon compiler structure in the Genesil system, with 0.8-/spl mu/m CMOS technology.