A 10-bit 500 MSPS segmented DAC with distributed octal biasing scheme
The effect of bias node voltage fluctuations on the performance of the current steering (CS) DAC is studied in this work. For that purpose a 10-bit segmented CS-DAC has been designed in 0.18 μm CMOS n-well technology provided by National Semiconductor. All current sources connected to the same bias cell act as correlated noise sources and generates more nonlinearity at the output. To improve the spurious free dynamic range (SFDR) of the DAC a new octal biasing technique is used in this paper. In the octal biasing technique 8-bias cells are used and they are placed in a 4×2 array structure. There is no direct connection between any two bias cells and they are considered as non-correlated cells. Thus the octal biasing and the non-correlated current sources help to reduce the noise and the input code dependent nonlinearities at the output. In Monte Carlo mismatch simulation the proposed DAC achieves 60.83 dB SFDR for 15.136 MHz signal at 500 MSPS sampling rate. The DAC shows a Nyquist SFDR of 60.57 dB in for 500 MSPS sampling rate. The DAC consumes only 31.62 mW of power at Nyquist signal frequency for 500 MSPS sampling rate with 1.8 v supply.