The Design of a Large Point Reconfigured FFT Based on FPGA
In this paper, we present a design and implementation of a large points reconfigured FFT. This design utilizes one chip FPGA to implement FFT/IFFT operation of high-speed data stream, which adopts two-dimension, parallel and pipeline stream mode and implements the reconfiguration of FFT’s points. It adopts trigonometric function interpolation to compress the twiddle-factors, which can reduce the resources and depress the power of FPGA. This design can be used to implement reconfigured FFT operation which can be from 1K to 1M points. It reaches the requirement of high-speed digital signal process. This design implements large points and reconfigured FFT operation and the aim is to realize miniaturization and low-power.