ASPEN: An Asynchronous Signal Processor for Energy Efficient Sensor Nodes
For ubiquitous wireless sensor networks, there are three main requirements. The devices must be extremely small, consume very little operating power, and capable of distributed signal processing to enable in situ processing of sensed data at leaf nodes of the network. This paper presents the design of an Asynchronous Digital Signal Processor (ASPEN) to realize these goals. Using Quasi-delay insensitive (QDI) asynchronous templates in the processor core, the energy consumption per instruction is reduced, while performing Digital Signal Processor (DSP) tasks. The processor takes advantage of multiple functional blocks, which are activated only when an instruction requiring their use is found in the instruction queue. The primary processor pipeline resembles that of a microcontroller while other units remain dormant until an instruction using them arrives in the queue. Functional blocks implemented include an asynchronous FFT core and a DSP datapath. The processor has been designed in a commercial 90 nm process. It consumes less than 10 pJ/instruction for ALU computations, and up to 80 pJ/operation for instruction fetch and decode operations. The FFT unit consumes 132 pJ for a 16-point FFT.