Enhanced low power motion estimation VLSI architectures for video compression
Power consumption is very critical for portable video applications. During compression, the largest portion of power is consumed in the Motion Estimation part, which requires a huge amount of computation. This paper presents an architectural enhancement to reduce the power consumption during full-search block-matching (FSBM) motion estimation without sacrificing throughput or optimality. The proposed approach achieves these power savings by disabling portions of the architecture that perform unnecessary computations. A comparison between our enhancement and others is presented based on simulation and analytical analysis. Different benchmarks are used to test and compare the discussed architectures. Analytical and simulation results show the effectiveness of the enhancements.