A Mostly Digital PWM-Based $\Delta\Sigma$ ADC With an Inherently Matched Multibit Quantizer/DAC
A mostly digital pulsewidth-modulator-based delta-sigma (ΔΣ) analog-to-digital converter is proposed. This system takes advantage of the duration of pulses, rather than voltage or current, as the analog operand used in its closed-loop operation. Therefore, circuits that process the pulses are digital in nature and improve with scaling. Furthermore, the architecture allows inherently matched multibit quantizer/digital-to-analog converter (DAC) blocks by taking advantage of delay lines reusable in both quantization and DAC operation. A second novelty of this architecture is the modulator's adaptive excess delay, which synchronizes the asynchronous loop with an external reference clock. This mitigates the problems associated with nonuniform sampling. A first-order 3-b prototype of this architecture is presented. The core occupies an area of 0.0275 mm2 in a 0.18-μm CMOS process, consumes 2.7 mW, and measures a 45.1-dB SNR over a 2-MHz bandwidth.