A 36nV/√Hz noise PSD chopper-stabilized CMOS amplifier with a new ripple-spur-filter scheme
A low-noise, low-power CMOS amplifier is developed using the chopper-stabilized technique. A new filter scheme is employed to suppress chopping ripple and spur. It composes of a band-pass amplifier, a novel low-pass-chopper (LPC) and a low-pass class-AB output stage. With the LPC, the amplifier rejects unexpected high frequency signal by about extra -12dB, which shares burden of the band-pass amplifier. The proposed amplifier is simulated in TSMC 0.35-μm CMOS process and a noise PSD of 36nV/√Hz and a unity gain bandwidth of 1MHz with an overall current consumption of 14.5μA are achieved.