RRNS quasi-chaotic coding and its FPGA implementation
In this paper, a new architecture of the redundant residue number system (RRNS) based quasi-chaotic coding is proposed for the secure telecommunication systems and networks. In the proposed architecture, a number of modulo operations required by the existing designs are replaced by binary coding operations to simplify the design. Also, a moduli selection method and a residue-to-binary converter with error-correction capability are proposed to further improve the efficiency of the design specifically for FPGA implementation. The proposed architecture is implemented and tested using Matlab and Xilinx FPGA hardware. The results show that compared to the existing design, the proposed design requires only 80% of the hardware resources while maintaining the same speed. The power consumption is also reduced by 25%.