A high-speed CMOS full-adder cell using a new circuit design technique-adaptively-biased pseudo-NMOS logic
A circuit design technique called adaptively biased pseudo-NMOS logic (APNL) is investigated and used in a differential-type full-adder cell design. Based on the layout and simulation results, the APNL full-adder cell is nearly 80% faster than conventional cascode voltage switch logic (CVSL) and over 30% faster than the domino CVSL circuits, while consuming comparable power and silicon area. An application example of the APNL technique is described.<<ETX>>