Fault tolerant techniques for TSV-based interconnects in 3-D ICs
TSV-based 3-D IC is one of the most promising approach in modern integrated circuit design. As TSV enables the integration of different dies with different technologies, it is considered as one of the key elements in IC design. Reliability of TSV is an important issue which needs to be addressed very carefully since a faulty TSV can result in the failure of the whole stack. TSV open defect alongside TSV short are the most prevalent faults in 3-D ICs. They can happen during TSV filling, bonding process or as a result of aging due to Electromigration. In this paper, we present two methods for reducing the amount of delay caused by a partially open TSV and TSV short defect in 3D-ICs. Simulation results demonstrate the effectiveness of the proposed method in improving the performance of 3-D ICs in presence of partially open and short TSV defects.