Design and implementation of a high resolution DPWM based on a low-cost FPGA
This paper proposes a new implementation method which can achieve DPWM with time resolution under 100ps. Utilizing the carry flag delay time, a high resolution DPWM can be achieved by low cost FPGA. The proposed DPWM method is, in principle, intended for FPGA implementation, but it can achieve high time resolution DPWMS and can be implemented in low cost FPGA. Linearity was manually optimized using the presented technique which reduces the non-linearity error. The proposed DPWM with 15-bit and 70–80ps resolution with a switching frequency of 1 MHz has been successfully implemented on a low-cost Atera Cyclone-II series FPGA.