Hardware implementation of adder for pulse signal processing
Analog to pulse converter (APC) converts continuous time signals into train of pulses such that each pulse interval represents a constant area. Recently, it was theoretically shown that arithmetic can be performed with pulse trains. In this paper, we examine the hardware design challenges in pulse signal processing when compared with conventional digital processing techniques and propose an architecture for implementation of pulse adders. The proposed architecture is validated for accuracy and we study the tradeoffs associated with the design parameters. Synthesis results show that a 16bit pulse adder occupies an area of 0374mm2 and consumes power of 3.06mW at 100MHz in SMIC 0.18ßm CMOS technology.