Design and Implementation of JPEG 2000 Codec with Bit-Plane Scalable Architecture
In this paper, an area-efficient JPEG 2000 codec is implemented on 6.1 mm2 with 0.18 mum CMOS technology dissipating 180 mW at 1.8 V and 60 MHz. It is capable of processing 78 MS/s for lossy coding at 1 bpp and 50 MS/s for lossless coding. Four techniques are used to implement this chip. The pre-compress ion rate-distortion optimization (pre-RDO) determines truncation points before coding to reduce computations for the EBC. The dataflow conversion and embedded compression reduces the tile memory bandwidth. The bit-plane parallel context formation enables scalable bit-plane coding. Experimental results show this chip has higher area efficiency than the previous works