Field-programmable gate-array-based investigation of the error floor of low-density parity check codes for magnetic recording channels
Good performance of iterative detection and decoding using low-density parity check (LDPC) codes has stimulated great interest in the data storage industry. One major concern in using LDPC codes in the read channel is their error floor, which is still an open question. To investigate the performance of LDPC codes in low bit-error rates (BER/spl sim/10/sup -10/), we developed a high-throughput fully reconfigurable simulator using a field programmable gate array. Using this simulator, we are able to observe the performance of LDPC codes at low BER within a reasonably short time (10/sup -10/ within 1.5 h). We show the evaluation results for two types of LDPC codes.