A bus-monitoring model for MPEG video decoder design
The variety of macroblock types and variable-length codes has increased the difficulty in predicting memory accesses and bus utilization pattern for accessing compressed data or pixels to/from external RAMs during the MPEG video decoding process. In this paper, we present a model and a simulator to aid MPEG decoder design by providing useful statistics related to bus utilization and waiting cycles. The model explores MPEG decoder architecture and data nature; it provides results to analyze bus bandwidth and determine proper sizes of decoder I/O buffers connected to the bus. Simulation is performed to test out different bus arbitration schemes for MP@ML data in MPEG-2 decoding.