Analysis and design of power hardware-in-the-loop testing for 400-Hz inverters
For the testing of 400-Hz inverters, a power hardware-in-the-loop (PHIL) platform is presented. However, the selections of power interface circuit parameters, such as filter of hardware interface (HI) and operating DC bus voltage of power amplifier (PA), remarkably affect the performance of the PHIL system. To solve this problem, an analytical and quantitative design method for power interface of PHIL is proposed. With the proposed design method, the relationships of the power interface circuit parameters and the PHIL system performances can be sufficiently taken into account and intuitively illustrated on a graph. Hence, the choices and optimizations of these parameters can be convenient and explicit. Moreover, a PHIL setup is built for testing a 400-Hz inverter to verify the effectiveness of the design method. Simulation and experimental results indicate that the setup achieves good performance.