Self-timed triple-rail MOS current mode logic pipeline for power-on-demand design
This paper presents an approach to address the high static power consumption problem of the MOS current mode logic (MCML) by integrating MCML with self-timed pipelines. We develop a new MCML style, called triple-rail MOS current mode logic (Tr-MCML), that supports seamless integration with a self-timed pipeline. A look-ahead self-timed Tr-MCML pipeline architecture is designed to realize the data-driven power-on-demand operation to reduce the static power consumption while maintaining the high-speed property of MCML. This design approach is particularly desirable for latency-critical digital systems that solely rely on high-speed circuit design to improve performance. We use ripple carry adders as a test vehicle to demonstrate the significant improvement on the energy-delay product (EDP) compared with conventional MCML design.