A VLSI architecture for radix-2/sup k/ Viterbi decoding with transpose algorithm
The paper presents a novel transpose path metric (TPM) algorithm to reduce the interconnection routing complexity for a radix-2/sup k/ Viterbi decoder. With simple local interconnections, the algorithm can provide a permutation function for state rearrangement in a transpose strategy. With features of modulation and regularity, this algorithm is very suitable for VLSI implementation; consequently, a larger memory length VA decoder can be constructed with several smaller memory length modules. Finally, a VLSI architecture for a 16-states radix-4 VA decoder using TPM has been developed.