A Bus-monitoring Model For MPEG Decoder Design
In MPEG video decoder design, the variety of macroblock types and variable-length codes has increased the difJiculty in predicting memoiy accesses and bus utilization pattern for accessing compressed data or pixels toJroom external RAMS during the decoding process. In this paper, we present a model and a simulator to aid MPEG decoder design by providing useful statistics related to bus utilization and waiting cycles. The model explores MPEG decoder architecture and data nature; it provides results to optimize bus and buffer design in MPEG decoding. Simulation is peformed to test out different bus arbitration schemes for MP@ML data in MPEG-2 decoding.