Novel design methodology for high-performance XOR-XNOR circuit design
As we scale down to deep submicron (DSM) technology, noise is becoming a metric of equal importance as power, speed, and area. Smaller feature sizes, low voltage, and high frequency are some of the characteristics for DSM circuits. A novel design methodology for the design of energy-efficient noise-tolerant XOR-XNOR circuits that can operate at low voltages is proposed. The proposed circuits are characterized and compared with previously published circuits for reliability and energy efficiency. To test their driving capability, the proposed gates are implanted in an existing 5-2 compressor design and are shown to provide superior performance. The average noise threshold energy is used for quantifying the noise immunity. Simulation results show that the proposed circuits are more noise-immune and displays better power consumption results as well as power-delay product characteristics. Also, the circuits prove to be faster and successfully work at all ranges of supply voltage starting from 0.6 V to 3.3 V.