Fault diagnosis and reconfiguration for reliable VLSI arrays
An online fault-tolerant strategy is proposed; it is composed of two phases: testing and locating faults, and reconfiguration. In the first phase, an online testing technique is used, which is a compromise between the commonly used techniques of time and space redundancy. It is capable of detecting permanent as well as transient faults. The reconfiguration phase is realized by using a global control. Switches are used to bypass the faulty processing element (PE). Backtracking is introduced into the algorithm for maximizing the processor utilization, at the same time keeping the complexity of the interconnection circuitry as simple as possible.<<ETX>>