The Failure Mechanism of Gate Resistance Testing for Power MOSFET
The vertical DMOS (double diffused MOSFET) is widely used in power microelectronics, its switching performance is determined mainly by the gate resistance and the input capacitance. Thus a gate resistance testing technique is developed in order to determine its device functionality. In this paper the authors discuss various processes induced device failures, such as the poor interconnect of the poly gate and the metal, the bonding wire, and the etch process, and their impact to the performance and reliability of the devices as well as the in-line testing method used for the performance validation