A 5mW MPEG4 SP encoder with 2D bandwidth-sharing motion estimation for mobile applications
A 5mW MPEG4 SP encoder is implemented on a 7.7mm2 die in 0.18mum CMOS technology. It encodes CIF 30frames/s in real-time at 9.5MHz using 5mW at 1.3V and VGA 30frames/s at 28.5MHz uses 18mW at 1.4V. This chip employs a 2D bandwidth-sharing ME design, content-aware DCT/IDCT, and clock gating techniques to minimize power consumption