A novel design of dual ladder resistor D/A converter
This paper presents a novel dual ladder resistor D/A converter architecture. A 10 bits D/A converter is implemented which is based on this architecture. The present architecture provides a novel decoding scheme for dual ladder resistor D/A converter that reduces the size of the decoding logic, reduces the number of switches in coarse resistor stage and fine resistor stage. Experience of the 10 bits D/A converter design was shared. The design achieves INL and DNL of +0.3/−0.4LSB, +0.5/−0.4 LSB. This 10 bits D/A converter was used in reference voltage source chip which was taped out by Chartered 0.35μm CMOS 2P4M Mixed-mode process.