A new leakage-tolerant domino circuit for wide fan-in gates with CNTFET
In this paper, a new leakage-tolerant domino circuit is presented which has lower power consumption and higher noise immunity without significant delay increment for wide fan-in gates. In the proposed technique, the voltage swing of the dynamic node can be reduced to decrease the power consumption caused by the heavy switching capacitance in wide fan-in gates. The simulation is provided with 64-input wide OR gates using a 32 nm CNTFET technology model. The simulation results are compared with CMOS of standard domino circuits at the same delay, and 98.4% power consumption reduction and 6.8 × Noise-immunity improvement are observed.