An FPGA implementation of a time-to-digital converter with a ring oscillator and buffers
A Time-to-Digital Converter (TDC) is widely used in applications that need to measure the time interval between events. Previous designs based on a feedback loop and an extended delay line suffer from poor accuracy caused by the non-linearity of a delay line. To overcome the poor accuracy in the previous TDC, this paper proposes a novel TDC that uses a ring oscillator to measure the interval by counting the number of cycles in the interval. To reduce the precision drop by the measurement with the ring oscillator, an additional delay line is used in the TDC. The proposed TDC is implemented by using Xilinx Spartan-6 LX9 FPGA with 20MHz oscillator.