A low power 10-transistor full adder cell for embedded architectures
A high performance Full adder cell has been designed using 10 transistors. The proposed cell has the advantage of low power consumption and high operating speed. Moreover, it occupies small area due to the small transistor count. The low power objective is achieved at the circuit level by reducing the number of internal node capacitances, by eliminating direct paths between the supply voltage and the ground, and by maintaining low switching activity in the circuit. The circuit is prototyped using 0.35 /spl mu/m CMOS technology using Cadence development tools and simulated using Hspice. The circuit consumes 0.752*10/sup -4/ Watt at a frequency of 500 MHz. The proposed cell is compared with both the standard Transmission Gate adder cell and a 16-transistor adder cell that was recently developed and characterized by its low power consumption compared to other adder cells. A 4-bit multiplier is constructed using the proposed adder cell and used as a test vehicle to check the performance of the new proposed design in embedded architectures.