A Novel Synthesizing Genetic Logic Circuit: Frequency Multiplier
This paper presents a novel synthesizing genetic logic circuit design based on an existing synthetic genetic oscillator, which provides a function of frequency multiplier to synthesize a clock signal whose frequency is a multiple of that of the genetic oscillator. In the renowned literature, the synthetic genetic oscillator, known as a repressilator, has been successfully built in Escherichia coli to generate a periodic oscillating phenomenon through three repressive genes repress each other in a chain. On the basis of this fact, our proposed genetic frequency multiplier circuit utilizes genetic Buffers in series with a waveform-shaping circuit to reshape the genetic oscillation signal into a crisp logic clock signal. By regulating different threshold levels in the Buffer, the time length of logic high/low levels in a fundamental sinusoidal wave can be engineered to pulse-width-modulated (PWM) signals with various duty cycles. Integrating some of genetic logic XOR gates and PWM signals from the output of the Buffers, a genetic frequency multiplier circuit can be created and the clock signal with the integer-fold of frequency of the genetic oscillator is generated. The synthesized signal can be used in triggering the downstream digital genetic logic circuits. Simulation results show the applicability of the proposed idea.