High speed, flexible, robust and low power processing approach
We are all longing for high speed, flexible, robust and low power processing system in the world. FPGA architecture is gathering attention due to one order less magnitude of power saving as one of non-Neumann approach. Other approach is like unified block included small logic, small memory and small controller which is announced by eASIC, nextrame-2/3(1) or Synopsis, EVP(2) as examples which are instead of many core Neumann architecture. These trends originate due to extremely lower power operation and elimination of band width wall between logic and memory. Our study is also for the same unified block that makes only memory with look up table (LUT) and small controller configuration(3). Using no logic circuit means LUT instead that is named “Memory-Logic Conjugated System (MLCS)”. The key of the concept is to make minimal function cluster of LUT array by SRAM circuit base that is significant to keep the highest efficiency. This can be seen one time to logic and other time to memory depending on the dynamical change of need. Dynamic reconfiguration can be led in only several clocks, that produces flexible system. Huge or tinny configurations are designed fairly easy to proper block arrangement by each application. These are also coming true redundant systems followed robust. As constructed memory, running power is very low as two orders less of magnitude than Neumann processor. High speed processing can be done by elimination of the band width wall because neighboring block job area is easy to communicate with each other. This will be presented with some of detail.