Precharged SRAM cell for ultra low-power on-chip cache
This paper proposes an ultra low-power technique to reduce dynamic and leakage power in SRAM. At write mode, the technique reduces the voltage swing required on the bit lines and depends on the cell itself to amplify the small swing to full swing. HSPICE simulation shows 94.2% write power saving in 0.18nm technology. On the sleep mode, the proposed cell reduces the leakage current by 60% for 70nm technology.