Design of a multi-frequency clocking circuit on an FPGA and analysis of its EMI emission
In this paper, we present a circuit design of multi-frequency clocking for reducing electromagnetic interference (EMI). First, we propose a generalized multi-frequency clocking (MFC) circuit. Then, to evaluate its impact on EMI reduction, we design a simple synchronous circuit with the proposed MFC scheme. Our design is implemented in a commercial Xilinx FPGA Spartan-3 device. Our approach shows that we achieve 1.3 dB, 4 dB, 5.7dB of EMI reduction with the MFC employing 2-frequency, 4-frequency, and 8-frequency components, respectively when compared to the single frequency clocking in synchronous circuit.