Record high mobility (428cm2/V-s) of CVD-grown Ge/strained Ge0.91Sn0.09/Ge quantum well p-MOSFETs
It is the first time that CVD-grown GeSn channels with low thermal budget of 400°C significantly outperforms the Ge channel processed at high thermal budget of 550°C. Low thermal budget is necessary to prevent the Sn loss during the process. Note that only MBE-grown GeSn had large mobility reportedly in the past. Even with high Sn content (9%), the strong photoluminescence is observed from GeSn layers on Ge buffer on 300mm Si (001), indicating the high crystalline quality by CVD epitaxy. Ge cap with significant Δ Ev at Ge/GeSn interface can ensure the gate stack quality, and reduce the scattering of holes in the GeSn quantum wells by oxide/interface charges and surface roughness. However, the mobility is degraded by thick cap due to low hole population in the GeSn wells. The ∼7% mobility enhancement on <110> channel direction is observed using external transverse uniaxial tensile strain of ∼0.11% due to the reduction of effective mass. The mobility of GeSn QW p-MOSFETs increases with decreasing temperature at both high and low inversion carrier density, indicating that the mobility is dominated by phonon scattering. On the contrary, Ge channels are dominated by Coulomb scattering at low inversion carrier density, which has decreasing mobility with decreasing temperature. The normalized noise power density of GeSn p-MOSFETs decreases with increasing Ge cap thickness, reportedly for the first time, indicating that the carrier number fluctuation and correlated mobility fluctuation can be reduced when the carriers are away from interface.