Characteristics of sub-1 nm CVD HfO/sub 2/ gate dielectrics with HfN electrodes for advanced CMOS applications
High quality thermal robust CVD-HfO/sub 2/ gate dielectrics with HfN electrodes were fabricated. The scalability of the HfN/HfO/sub 2/ gate stack and the integration issues with CMOS devices were systematically investigated. The equivalent oxide thickness (EOT) is aggressively scaled down to 0.65 nm with low gate leakage and excellent reliability characteristics. High performance HfN/HfO: gated nMOSFET with 0.95 nm EOT was fabricated by using a gate-first process compatible with standard CMOS process flow. Significantly improved effective electron mobility is achieved in the device. The improved mobility is related to a high temperature post annealing process after HfO/sub 2/ deposition in the gate-first process such as the S/D activation annealing, which could effectively reduce the charge traps in HfO/sub 2/ films. A dual metal gate integration process for HfO/sub 2/ CMOS devices is demonstrated using a HfN dummy metal layer. In the process, the dummy HfN metal gate electrode was selectively removed from high-temperature annealed HfN/HfO: gate stack by diluted hydrofluoric without causing any degradation to the underlying HfO/sub 2/ gate dielectrics. Then two other metals with appropriate work functions for dual-gate CMOS, such as Ta for n-MOS and Ni for p-MOS were then re-deposited on HfO/sub 2/ as the new gate electrodes. The resulting n- and p-MOS devices show a work function difference of -0.8 eV.