Analysis and design of a 30 MHz resonant SEPIC converter
This paper presents the analysis and design of a resonant SEPIC converter operating at 30 MHz. With the conventional design method, tuning the amplitude and phase of the fundamental input voltage and current affect each other so that the design procedure is trial-and-error. An improved design method is proposed by re-dividing the resonant SEPIC topology and defining the new variables to realize the independent tuning of the amplitude and phase. The loss analysis is provided. A 15 V input, 14 W/28 V output, 30 MHz prototype has been built to verify the proposed design method. The prototype achieves the efficiency above 80% over a wide load. Furthermore, a novel structure of the PCB embedded inductors is used in a 25 W prototype to further improve the power density.