Power Deduction in Digital Signal Processing Circuit using Inventive CPL Subtractor Circuit
The proposed 4 bit subtracter circuit is designed by using bit slice method of complementary pass transistor logic (CPL), which is suitable for applications like fast shifting; multiplier/adder in the loop cycle of DSP data processing device. The circuit can perform real time computational tasks at high speed. The designed circuit is performing efficiently in filtering signal at 100-520 MHz sampling rate in real time. We have analyzed the proposed circuit for submicron regime, whose layout is designed by using microwind III VLSI CAD tools, in terms of propagation delay, power consumption, power dissipation and area. In 50 nm analysis, the proposed circuit is found to dissipate less power (~0.46 muW) and possess less overall area of order of 423 mum2. The propagation delay is 9.5206 times 10-12 sec. In DSP architecture, time and area are the critical components which are responsible for the efficient execution of arithmetic and logical operation. Our proposed circuit is enhancing, complete set of instruction cycle, passing at speed of 9.0 GHz, which is higher than reported results.