A 10-transistor low-power high-speed full adder cell
In this paper, we introduce a high-speed low-power 10-transistor 1-bit full adder cell. The critical path consists of an XOR gate; an inverter and one pass transistor. A prototype of the proposed adder cell in 0.6 /spl mu/m CMOS technology has an average delay time of 0.084 ns. It also exhibits low average power dissipation of 0.891/spl times/10/sup -4/ watt at frequency equal to one GHz. In an n-bit adder circuit, the new adder cell will give alternate polarity for the carryout in the odd and even positions. The inverters in the structure of the proposed FA cell act as drivers. Therefore, each stage will not suffer a degradation in its deriving capabilities. This saves power, area, and time. The new cell is used to build a prototype for a 32-bit ripple carry adder. This prototype has 384 transistors and it operates at 2.8 V with an average delay of 4.1 ns, and a low power dissipation of 2.6 mW at frequency equal to 250 MHz.