Design of concurrent error-detectable VLSI-based array dividers
A building-block design for VLSI-based array dividers with concurrent error detection by recomputing using partitioned architecture (REPA) is proposed. The basic concept is that the divide array can be divided into two identical parts and its operation can be completed by using one part through two iterative calculations. With two such parts, a concurrent error detection scheme based on a space redundancy approach can be designed, and error detection is achieved at each iteration. The design is better than previous designs in terms of area requirement, time penalty, error detection capability, and detection period. Advanced analysis with m partitions is included. The experimental results are attractive, especially for certain designs with application-specified tradeoffs between speed performance and area cost.<<ETX>>