Post-Silicon Clock-nvert (PSCI) for reducing process-variation induced skew in buffered clock networks
Proposed in this paper is a post-silicon technique and circuits that reduce random process-variation induced skew with simple leaf buffers modification of a buffered clock network. If a timing violation due to clock skew occurs during testing, the present technique offers a second chance via Post-Silicon Clock-Invert (PSCI), which decreases the probability of having errors due to clock skew thus increasing timing yield or design performance. In the cases where the clock frequency of each chip is adjusted post-silicon to deal with inter-die process variations, this technique allows significant number of chips to operate at higher frequencies. The present technique does not require any modifications to the clock network and repower buffers, thus it has negligible area, power, and design overheads, and its post-silicon activity is simple and fast. Evaluated via Monte-Carlo simulation in the context of a 16 leaves buffered H-Tree topology in a 10-mm×10-mm synchronous region, PSCI shows an improvement of 19.56%, 28.39%, and 30.3% in the global clock skew mean, standard deviation, and worst case, respectively.