On-chip learning for a scalable hybrid neural architecture
A new class of neural architecture with on-chip learning has been developed. Learning has been implemented in analog while the control is performed in digital. An efficient analog technique has been developed to refresh the capacitors that store the synaptic weights. The graded update signals are also generated in analog, it is added to the weights via simple local analog adders. This localization of weight update makes the complexity of the learning procedure independent of the overall network size. The new ar chitecture is based on a computational kernel composed of two chips; the SynChip and NeuChip. The SynChip consists of an array of 32/spl times/32 analog synapse modules (SynMod), a digital control block (SynLogic), a voltage reference of 16 levels, and 32 refreshing blocks (RefMod). The NeuChip consists of a 32 analog neurons modules (NeuMod) and a digital control black (NeuLogic). This two-chip set can be cascaded on a regular grid to build large size neural networks.