A systematic framework for high throughput MAP decoder VLSI architectures
The paper presents a systematic method for the development of high throughput MAP decoder architectures. High throughput is achieved by exploiting more algorithmic parallelism. The paper proposes the use of the trellis-time graph to study the parallel MAP decoder architectures analytically. A parameterized windowing approach is developed to construct the trellis-time graph of the decoding operation. Next, an exhaustive search is used to explore the parallelism vs. hardware resources systematically. This method is applied towards the design of a MAP decoder that has a frame of size 320 bits. A tradeoff among the decoding delay, number of kernels, number of BMM banks, and number of SMM banks is presented.