Geometric programming based power-delay optimization using transistor-sizing for submicron and deep submicron CMOS inverter
This paper proposes a new method to formulate the transistor sizing problem as a geometric programming by using a modified I-V model in the power-delay product (PDP), for sub micron and deep sub micron CMOS inverter circuits. The design objective and constraints are modeled as posynomial functions of the design variables. The model has been solved efficiently, which generates a number of important practical consequences. This method computes the absolute limit of performance for given input frequency and load capacitance of a transistor and technology parameters. The accuracy of performance prediction in the transistor-sizing (through geometric programming) problem is verified due to its closeness to SPICE simulation (0.25-/spl mu/m) results. Further the approach has been extended to predict the transistor sizing for deep submicron (0.09-/spl mu/m) CMOS inverter.