A scalable systolic array architecture for the 2D discrete wavelet transform
Summary form only given, as follows. A systematic synthesis approach has been applied to the 2D discrete wavelet transform (DWT), and a scalable systolic array architecture has been derived based on the data dependence analysis and linear index space transformation. The architecture has regular topology, local routing, simple controller and high throughput rate, and it can be easily extended to different parameters of various levels, macroblocks and filters. The architecture has been implemented on Cadence Edge Framework.