Ultra low power 1-bit adder cells
Supply voltage scaling is considered to be an effective technique for reducing power consumption of digital CMOS circuits. But such approach has a detrimental effect on system performance, which renders it impractical for many applications. However, in some applications, where power consumption is of critical importance, supply voltage scaling can be reasonably effective. In this paper power critical applications are considered and a set of adders is presented. The supply voltage scaling technique is applied and different adders are analyzed for a range of supply voltage levels (1.8-0.15 Volts). It is found that at very low supply voltage levels, the performance experiences immense deterioration. Moreover, for a fixed frequency of operation, the lowest supply voltage level attainable depends on circuit structure.