Real-time deblocking filter for MPEG-4 systems
This paper presents a deblocking filter architecture in the MPEG-4 standard. This architecture performs as a 1D nonlinear filter across the block boundary to efficiently suppress blocking artifacts. Two shift register banks are used in the design; their use greatly reduces the control complexity of data flow. Due to efficient scheduling, the size of storage and the total clock cycles are minimized. The maximum processing rate of this architecture mapped in 0.35 /spl mu/m technology is 30 Mpixels/sec, which can support NTSC resolution at 30 frames per second. The power consumption of the design is 46.6 mW while operating frequency is 81 MHz.