Chip-to-wafer (C2W) 3D integration with well-controlled template alignment and wafer-level bonding
This paper presents on a novel chip-to-wafer (C2W) three-dimensional (3D) integration technology with well-controlled template alignment and wafer-level bonding, enabling precise alignment, few thermal cycles and high throughput of 3D system fabrication. The key processes are investigated and discussed in detail, including chip edge definition, template fabrication, C2W alignment and wafer-level bonding. The C2W 3D integration technology is successfully demonstrated using Cu daisy chains, a patterned thick benzocyclobutene (BCB) layer on the wafer as the alignment template, and wafer-level C2W Cu-Cu bonding. An alignment accuracy less than 2 μm is achieved. The FIB-SEM images reveal that Cu grains cross the original Cu-Cu bonding interface to form strong bonding. The measured I-V characteristics of daisy chains show a linear ohmic behavior, and the specific contact resistance of Cu-Cu bonding structures is on the order of 10−8 ohm-cm2, suggesting good electric contacts.