A 15-bit two-step sigma-delta ADC with embedded compression for image sensor array
This paper presents a novel incremental Σ-Δ ADC using two-step conversion and the fully-floating double-sampling integrator to greatly reduce the converting time. With a special procedure to solve the accuracy loss problem, the resolution of ADC is improved by one bit at the same time. What's more, another comparison is added during the conversion to detect redundant pixels in the image so that data compression is achieved in a simple way.