B-spline factorization-based architecture for inverse discrete wavelet transform
In this paper, the VLSI architecture for the inverse discrete wavelet transform (IDWT) is proposed on the basis of B-spline factorization that is the intrinsic property of DWT and comprises two parts: B-spline part and distributed part. After the polyphase decomposition, the former can be constructed by Pascal or direct implementation. And the latter one can be implemented by serial or parallel filter architecture. The B-spline-based architectures can reduce multipliers but would introduce additional adders compared with convolution-based architectures. Because the hardware complexity of adders is much less than that of multipliers, B-spline-based architectures could provide smaller hardware complexity for DWT and IDWT. The case study of the (10,18) filter will also be given to demonstrate the efficiency.