Matching graph connectivity of LDPC codes to high-order modulation by bit interleaving
The decoding threshold and the error floor are two key performance metrics that are commonly used to evaluate the goodness of a LDPC code design. For a finite-length irregular LDPC code employing sub-optimal iterative decoding algorithm, the major factors that determine the decoding threshold and the error floor are nodes degree distribution as well as the edge permutation associated with its tanner graph. In addition, due to the non-uniform bitwise error protection inherent to a high-order constellation (e.g. 256-QAM, 1024-QAM), generally there exists a mismatch between the encoder and the modulator unless a dedicated ldquoouterrdquo bit interleaver (de-multiplexer) is plugged between the two modules to match the non-uniform bits reliability. Motivated by the requirement for high spectral efficiency in the development of future DVB-C standard as well as the industrial trend for reusing the LDPC codes standardized in DVB-S2 specification, in this paper we focus on the design of the ldquoouterrdquo bit interleaver, assuming the LDPC code and the order 22Q constellation mapper are fixed a priori. The configuration for the proposed bit interleaver is solved by optimizing the degree profiles of Q ldquosubcodesrdquo, subject to the constraints of the degree distribution given by the ldquomotherrdquo code. Besides, to prevent the error-prone patterns existing in the ldquomotherrdquo code to cause decoding failures, an extra constraint is imposed on the allocation of low-degree coded bits to the constellation mapper. Compared with the random interleaving approach, the proposed bit interleaver can achieve significant gains in both the waterfall and the error floor regions.