Complex reliability evaluation of voters for fault tolerant designs
Hardware voters are bit voters computing a majority of n input bits. An m-out-of-n hardware bit voter is a circuit with n bit inputs, and 1 bit output y, such that y=1 if at least m-out-of-n inputs bits have the value 1. A hardware voter can be constructed as two level AND-OR (equivalently OR-AND and other structures) using CMOS VLSI technology. The goal of the paper is to present reliability estimations, failure modes and effects and criticality analysis (FMECA) of voting networks at the transistor level, in CMOS VLSl implementation. FMECA is performed using the functional tree of the system, representing the data flow from the lowest level functional block up to the higher level functional blocks. The main idea of this research is to identify the best designs of voting circuits in terms of reliability parameters and to identify their critical failures and effects.