An array optimization algorithm for VLSI layout
The authors propose a new array optimization algorithm which is used to minimize the quadratic architectures in VLSI cell generation. Instead of using simulated annealing technology, they use a deterministic strategy to minimize the area usage. The experimental results indicate that their algorithm, like simulated annealing algorithms, has the property of climbing out of local optimums. However, it requires much less computing time. Some published examples were tested. The results are promising.<<ETX>>