The chip design of a 32-b logarithmic number system
To design a 32-bit logarithmic number system (LNS) processor, this paper presents two novel techniques: Digit-Partition (DP) to design log/sub 2/(1.x) function and Iterative Difference by Linear Approximation (IDLA) to design 2/sup 0.x/ function. The experimental result reveals that the proposed design is more attractive than the previous researches in the LNS processor.<<ETX>>