A high performance Full Adder based on Ballistic Deflection Transistor technology
In this paper, we propose a 1-bit Full Adder circuit built with Ballistic Deflection Transistors (BDT). BDT is a disruptive technology based on AlGaAs/InGaAs heterostructure. Different combinational circuits were successfully realized using BDT NAND gate and General Purpose Gate (GPG) structures. The developed circuit is an extension of BDT GPG and different from that of the previously implemented adder circuit. The proposed Adder consists of Sum and Carryout structures, comprising seven and five BDTs, respectively. Monte Carlo modeling of a BDT NAND Gate, which consists of associating two BDTs, has been performed and the obtained I-V characteristics were integrated with Verilog AMS to investigate the feasibility of the proposed circuit. Simulation results performed on Cadence Spectre simulator indicate the correct functionality of the proposed full adder.