Hardware JPEG Decoder and Efficient Post-Processing Functions for Embedded Application
In this paper, a hardware JPEG decoder with three post-processing functions is proposed for embedded application. This decoder could decode the sequential JPEG image except for arithmetic encoding and 12bit sample precision. The post-processing functions - Inner Down-Scaling (IDS), Region-Of-Interest (ROI) decoding and Partial DeCoding (PDC) are employed to make an efficient post-processing for the embedded applications. It is a fully pipelined design with friendly interface, which makes it easier to be integrated into the SoC system. The decoder has been implemented with TSMC 55nm technology. The equivalent gate count including memories is about 206K and the max work frequency is about 325MHz.