Vertically Stacked Strained 3-GeSn-Nanosheet pGAAFETs on Si Using GeSn/Ge CVD Epitaxial Growth and the Optimum Selective Channel Release Process
Fully compressively strained GeSn quantum-well channels sandwiched by Ge sacrificial layers on 200-mm silicon-on-insulator (SOI) wafers are grown using chemical vapor deposition. The transmission electron microscopy images indicate that dislocations are confined near the relaxed Ge buffer/SOI interface, resulting in low defect densities in the stacked GeSn channels. The top Ge cap is essential to ensure that the top GeSn channel matches the other two channels during the Ge etching. Channel release is obtained by etching of the Ge sacrificial layers with optimum ultrasonic-assisted H<sub>2</sub>O<sub>2</sub>. The low thermal budget gate-stack (400 °C) and S/D parasitic resistance reduction are achieved. The first stacked 3-Ge<sub>0.93</sub>Sn<sub>0.07</sub>-channel p-gate-all-around FET with <inline-formula> <tex-math notation="LaTeX">${L} _{\text {CH}}= 60$ </tex-math> </inline-formula> nm has a record high <inline-formula> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle ON}}=1975~\mu \text{A}/\mu \text{m}$ </tex-math> </inline-formula> (per channel width) at <inline-formula> <tex-math notation="LaTeX">${V}_{\text {OV}}={V}_{\text {DS}}=-1$ </tex-math> </inline-formula> V, among all GeSn pFETs. The junctionless device structure is used to simplify the process.