Cost-effective and low-power memory address bus encodings
This paper presents encoding methods that build on TO-encoding to achieve considerable reduction in memory address bus wires with small performance overhead, while reducing address bus switching activity. The known TO-encoding is combined with a variable cycle transmission technique that uses the TO's increment signal (INC) as an indicator of the number of cycles. Two of the proposed methods maintain the energy efficiency that is significantly reduced due to time-multiplexing. Benchmark experiments show that wire count of the instruction memory address bus can be reduced by around half at the price of 12.89% average performance penalty, while maintaining the low switching activity of the original TO-encoded bus.