Evolving Sorting Networks using Genetic Programming an Reconfigurable Xilinx 6216 Field-Programmable Gate Array
This paper describes how the massive parallelism of the rapidly reconfigurable Xilinx XC6216 FPGA (in conjunction with Virtual Computing Corporation's H.O.T. Works board) can be exploited to accelerate the computationally burdensome fitness measurement task of genetic algorithms and genetic programming. This acceleration is accomplished by embodying each individual of the evolving population into hnrdware in order to perform this time-consuming fitness measurement task. A 16-step sorting network for seven items was evolved that has two fewer steps than the sorting network described in the 1962 O'Connor and Nelson patent on sorting networks (and the same number of steps as a 7sorter that was devised by Floyd and Knuth subsequent to the patent and that is now known to be minimal).