A compact single-pass architecture for hysteresis thresholding and component labeling
Hysteresis thresholding offers enhanced edge/object detection in the presence of noise. However, due to its recursive nature, it requires a lot of memory and execution time. Thus, it is restricted and sometimes totally avoided in streaming processors with limited memory. We propose an efficient architecture coupling hysteresis thresholding with component labeling and feature extraction in a single pass over the image pixels. The operations are performed on the fly while recycling labels to avoid additional passes for handling candidate pixels and extracting object features. Moreover, only one row of compact labels is buffered. Hence, the execution speed of the algorithm is increased and the memory requirements are drastically reduced when compared to state of the art techniques. When implemented on FPGA, this technique promises to offer even more speed up and efficient resource utilization.