Reducing the switching activity of modified SAFF flip-flop for low power applications
The design and analysis of flip-flops is a critical issue in the design of high-performance and low power systems. In this paper, we propose a low power and a high-speed flip-flop (LP-SAFF) based on the Sense Amplifier Flip-Flop (SAFF). The saving in power consumption was achieved by reducing the switching activity at major internal nodes of the original SAFF. Our simulations show that this new flip-flop achieves major reduction in power consumption (25%-80%) and increases its performance by 5%-16%.