New method to extract interface states density at the back and the front gate interfaces of FDSOI transistors from CV-GV measurements
A novel method is proposed to extract interface state density Dit at both Front and Back Gate interfaces. This accurate technique based on CV and GV measurements, enables to measure low Dit densities ~10<sup>10</sup>traps/cm<sup>2</sup>/eV, at both interfaces on standard FDSOI transistors. In particular, it was found that DitBG is very low ~3.10<sup>10</sup> traps/cm<sup>2</sup>/eV, and about one decade smaller than Dit<inf>FG</inf>=5.10<sup>11</sup> traps/cm<sup>2</sup>/eV.