A 96 /spl times/ 64 intelligent digital pixel array with extended binary stochastic arithmetic
A chip architecture that integrates an optical sensor and a pixel level processing element based on binary stochastic arithmetic is proposed. The optical sensor is formed by an array of fully connected pixels, and each pixel contains a sensing element and a Pulse Frequency Modulator (PFM) converting the incident light to bit streams of identical pulses. The processing element is based on binary stochastic arithmetic to perform signal processing operations on the focal plane VLSI circuit. A 96 /spl times/ 64 CMOS image sensor is fabricated using 0.5/spl mu/m CMOS technology and achieves 29 /spl times/ 29/spl mu/m pixel size at 15% fill factor.