Inductive techniques for formal verification of systolic array designs in DSP applications
It is shown how several inductive techniques can be utilized to provide fast and efficient proofs to the correctness of systolic designs in digital signal processing (DSP) applications. These techniques exploit the repeatability, regularity, and locality nature of systolic arrays and algorithms in DSP to produce fast proofs independent of the array size. How inductive techniques can be applied to different array topologies suitable for DSP is also shown, and the structure of the verifier developed to automate induction using logic programming is illustrated.<<ETX>>