3D discrete wavelet transform architectures
Compression is a significant operation in many 3D data applications, such as magnetic resonance imaging (MRI), medical diagnosis, television, and seismic data. Employing standard 2D compression techniques do not offer efficient solutions in these applications. In this paper, a 3D discrete wavelet transform (DWT) approach is proposed for performing 3D compression. Two architectures are presented. The first architecture, called 3D-I, is a straight-forward implementation of the 3D DWT. It allows even distribution of the processing load onto 3 sets of filters, with each set doing the calculations for one dimension. The filters are easily scalable to a larger size. The control for this design is very simple, since the data are operated on in a row-column-slice fashion. The design is cascadable. Due to pipelining, all filters are utilized 100% of the time, except for the start up and wind-down times. The second proposed architecture, 3D-II, uses block inputs to reduce the amount of on-chip memory. It has a control unit to select which coefficients to pass on to the low and high pass filters. The RAM on the chip is small compared to the input size, since it depends solely on the filter sizes. The filters are parallel, since systolic filters assume that the data is fed in a non-block form such that partial calculations are done.