On-chip picosecond delay measurement of RSFQ digital logic gates
Because RSFQ circuits are intended to operate at multi-GHz frequencies, a logical requirement for developing the technology is a method of accurately measuring the picosecond delays associated with individual logic circuits. A technique has been developed for on-chip measurements of such RSFQ gate delays. The central element in this scheme is a race between a path of calibrated variable delay and a path of unknown delay. Modification of the canonical RSFQ RS flip-flop circuit yields a multiple state destructive readout cell (MDRO), in which one can configure the number of flux quanta to be stored. This circuit has been experimentally verified for groups of two flux quanta. Used in concert with the confluence buffer, this scheme can provide the RSFQ designer with sub-picosecond pulse arrival delay information crucial for higher order circuit simulation. A detailed experimental process is presented from which this timing information can be extracted using basic low-speed measurement techniques.<<ETX>>