Low-cost, high-performance VLSI design of an MQ coder for JPEG 2000
Embedded block coding with optimized truncation (EBCOT) is a key algorithm in JPEG 2000 image compression system. In this algorithm, output generated by the bit plane coder (BPC) is supplied to an MQ coder. Though several high speed BPC architectures are available, overall performance EBCOT algorithm is getting restricted by the speed of an MQ coder. Therefore, we propose a high speed, area efficient VLSI architecture for an MQ coder. This pipelined design is implemented on Startix series FPGA and it operates at 153 MHz. The synthesis report demonstrates that as compared to existing designs, the requirement of logic- and memory-elements is reduced by about 71.53% and 59.3%, respectively. Throughput of the proposed MQ coder is 137.7 MS/s which is 1.85 times higher compared to the designs reported. The renormalization module is capable of operating at 326 MHz. So, coding efficiency can further be improved by using multiple clock domains.