Adder-accumulator cells in RSFQ logic
We are in the process of designing a Finite Impulse Response (FIR) filter for use in a Digital Signal Processing (DSP) system based entirely on Rapid Single Flux Quantum (RSFQ) logic. One aspect of this project involves the development of the arithmetic unit of the filter, in this case an adder-accumulator multiplier. This article describes two cells can perform the function of accumulated addition in the adder-accumulator multiplier. We have fabricated both cells and tested them at low speed.<<ETX>>