Asynchronous test hardware for Null Convention Logic
Asynchronous design is predicted to have a significant place in the future due to benefits of speed, power consumption, and design. Null Convention Logic (NCL) is a subcategory of asynchronous design that results in the most reliable and low-power asynchronous hardware. However, test strategies are not adopted to match the characteristics of this important asynchronous method, and the existing test methods for NCL use synchronous test hardware. In this paper asynchronous test hardware is proposed for testing NCL-based circuits to avoid problems of synchronous design as well as the need for asynchronous-synchronous interfaces and clock trees. The proposed test hardware is implemented in HDL and synthesised to define design characteristic and improvements over previous work.