VLSI implementation of MQ decoder in JPEG2000
JPEG2000 image compression system consists of two main algorithms namely, discrete wavelet transform (DWT) and embedded block coding with optimized truncation (EBCOT). These algorithms are compute intensive and require efficient VLSI implementation for real time applications. Bit plane coder (BPC) and MQ coder are the two cores of the EBCOT algorithm. All processes to be executed by the MQ coder are sequential in nature and hence restricts the speed of EBCOT. In this paper we propose a high speed and area efficient architecture of MQ decoder which is implemented on Virtex-2 FPGA. The implementation results show that the design operates at 142 MHz and hardware cost is very low. Estimated frame rate is 20.41 frames per second (FPS) at this frequency. On Virtex-5 device design operates at 222.8 MHz and estimated frame rate is 32.02 FPS. Hardware overhead is reduced to the great extent because shift register based renormalization unit is used which operates at high speed.