Effects of the Variation of ${V}_{\text {GS}}$ Sweep Range on the Performance of Negative Capacitance FETs
We report the first investigation of the impacts of gate voltage sweep range <inline-formula> <tex-math notation="LaTeX">${V}_{\text {GS,range}}$ </tex-math></inline-formula> on the performance of negative capacitance (NC) transistors. As <inline-formula> <tex-math notation="LaTeX">${V}_{\text {GS,range}}$ </tex-math></inline-formula> is reduced, NC GeSn pFETs generally exhibit an increased hysteresis or a transition from non-hysteretic to hysteretic, and show a degradation of <inline-formula> <tex-math notation="LaTeX">${I}_{\text {DS}}$ </tex-math></inline-formula>. This is due to the reduction of the ratio of remnant polarization <inline-formula> <tex-math notation="LaTeX">${P}_{\text {r}}$ </tex-math></inline-formula> to coercive field <inline-formula> <tex-math notation="LaTeX">${E}_{\text {c}}$ </tex-math></inline-formula> with the reduced voltage across the HZO. Interestingly, however, some NC devices show a negligible impact of <inline-formula> <tex-math notation="LaTeX">${V}_{\text {GS,range}}$ </tex-math></inline-formula> on hysteresis and <inline-formula> <tex-math notation="LaTeX">${I}_{\text {DS}}$ </tex-math></inline-formula>. The NC transistor demonstrates a stable hysteresis in 139–149 mV range and the improved SS and <inline-formula> <tex-math notation="LaTeX">${I}_{\text {DS}}$ </tex-math></inline-formula> over the control device, with a reduced <inline-formula> <tex-math notation="LaTeX">${V}_{\text {GS,range}}$ </tex-math></inline-formula> of 0.5 to −0.5 V. To obtain device performance independent of <inline-formula> <tex-math notation="LaTeX">${V}_{\text {GS,range}}$ </tex-math></inline-formula>, the ratio of <inline-formula> <tex-math notation="LaTeX">${P}_{\text {r}}/{E}_{\text {c}}$ </tex-math></inline-formula> of the HZO needs to stabilize in a very small <inline-formula> <tex-math notation="LaTeX">${V}_{\text {GS,range}}$ </tex-math></inline-formula>.