Design and implementation of double base integer encoder in the flash ADC
The DBNR (Double Base Number Representation) has been known to represent the Multidimensional Logarithmic Number System for implementing the multiplier accumulator architecture of DSP (Digital Signal Processing). This paper also uses the DBNR to improve the bottleneck of DSP arithmetic circuits with the flash ADC (Analog-to-Digital Converter). The Constraint algorithm is suggested to solve fan-in problem of the Greedy algorithm in designing encoder circuit of the flash ADC. The Constraint algorithm shows better performance in terms of layout area, power consumption, and operation speed, compared with the FAT tree encoder, which is known as the fastest encoder circuit yielding binary output.