A 53&#x00B5;W −82dBm sensitivity 920MHz OOK receiver design using bias switch technique on 65nm SOTB CMOS technology
This paper presents an ultra-low power receiver design at 920MHz. We proposed a receiver architecture, in which bias switch technique is applied to reduce power consumption significantly. The receiver was simulated and laid out on 65nm SOTB CMOS technology, consuming only 53μW at 0.6V supply voltage. It achieves a sensitivity of -82dBm with a data rate of 10 - 100 kbps.