Analysis of sub threshold leakage reduction techniques in deep sub micron regime for CMOS VLSI circuits
Leakage power dissipation has become major portion of total power consumption in the integrated device and is expected to grow exponentially in the next decade as per International Technology Roadmap for Semiconductors (IRTS). This directly affects the battery operated devices as it has long idle times. Thus by scaling down the threshold voltage has tremendously increased the sub threshold leakage current thereby making the static power dissipation very high. To overcome this problem several techniques has been proposed to overcome this high leakage power dissipation. A comprehensive survey and analysis of various leakage power minimization techniques is presented in this paper. Of the available techniques, eight techniques are considered for the analysis namely, Multi Threshold CMOS (MTCMOS), Super Cut-off CMOS (SCCMOS), Forced Transistor Stacking (FTS) and Sleepy Stack (SS), Sleepy keeper (SK), Dual Stack (DS), Input Vector Control (IVC) and LECTOR. From the results, it is observed that MTCMOS and SCCMOS techniques produces lower power dissipation than the other techniques due to the ability of power gating.