Glitch-Free Multi-Modulus Frequency Divider for Quantization Noise suppression in fractional-N PLLs
A novel frequency divider for Quantization Noise (QN) suppression in fractional-N phase-locked loops (PLLs) is presented in this paper. The proposed Multi-Modulus Frequency Divider (MMFD) utilizes a novel glitch-free divide-by-0.5/1/1.5/2 cell to reduce the frequency division step to 0.5 and the quantization noise induced by ΔΣ modulation is thus suppressed by additional 6dB. The circuit is designed and simulated in a 0.18µm CMOS process. The maximum input frequency is up to 3.8GHz across all variations of Process, supply Voltage and Temperature (PVT) and the current consumption is about 8mA from a 1.8V supply. Compared with other frequency dividers used for QN suppression, the proposed MMFD achieves 6dB QN suppression while consuming less power and operating at higher input frequency.