A MOS Transistor with Source/Drain on Insulator and Channel Doped in Step-Function Profile
A new MOS device design applied to the nano-scale is proposed. In this design, while the channel region is in the substrate, the source and drain regions except for the lateral sides connecting to the channel are insulated from the substrate. The insulated source/drain helps to reduce the junction capacitances and leakages, and potentially eliminate the punch-through between them. On the other hand, the channel region is doped in a step-function (extremely retrograde) profile to minimize the threshold voltage variations caused by dopant number fluctuations and the carrier mobility degradation related to the high electrical field in the channel region. The device characteristics of MOSFETs with the new design are compared with that of both bulk devices with super-halo doping profile in the channel and the Ultra Thin Body (UTB) SOI MOSFETs. The Simulated results show the new design provides nano-scale MOS devices with similar or better short channel effect immunity and sub-threshold characteristics to or than both super-halo and UTB schemes. A process for fabricating the device with the proposed design is also investigated.