gMRAM: Gain-cell magnetoresistive random access memory for high density embedded storage and in-situ computing
High density embedded memories have been demanded increasingly to enhance the performance and reduce the power dissipation of advanced systems, such as multicore processors, which have been used in a wide variety of applications from servers to Internet-of-things (IoT) devices. In this paper, a memory cell, referred to as the gain-cell magnetoresistive random access memory (gMRAM), is introduced. The gMRAM significantly reduces the cell area per bit as compared to state-of-the-art embedded memories, provides opportunities for the joint enhancement of performance and reduction of power dissipation, and provides a natural basis for in-situ computing. A gMRAM cell simultaneously retains two bits, a nonvolatile bit using a magnetic tunnel junction (MTJ) and a dynamic bit using the access transistor of the MTJ. The two bits are independently and nondestructively accessible for read and write. This paper focuses on the design and characterization of the gMRAM cell, array architecture, and read/write circuitry. Simulation results from an 8 kb gMRAM array using a 14 nm standard FinFET CMOS technology demonstrate a 750 ps / 475 ps access time for dynamic read/write, while the nonvolatile bit can be read from or written to the same cell with a, respectively, 750 ps and 3.5 ns access time. The gMRAM cell area per bit is 3× (2×) smaller than a SRAM (3T eDRAM) cell in the same technology.